Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS
- OVERVIEW
- DETAILED DESCRIPTION
- Fixed Frequency PWM Control
- Slope Compensation Output Current
- Pulse Skip Eco-Mode
- Low Dropout Operation and Bootstrap Voltage (BOOT)
- Error Amplifier
- Voltage Reference
- Adjusting the Output Voltage
- Enable and Adjusting Undervoltage Lockout
- Slow Start/Tracking Pin (SS/TR)
- Overload Recovery Circuit
- Sequencing
- Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- Overcurrent Protection and Frequency Shift
- Selecting the Switching Frequency
- How to Interface to RT/CLK Pin
- Power Good (PWRGD Pin)
- Overvoltage Transient Protection
- Thermal Shutdown
- Small Signal Model for Loop Response
- Simple Small Signal Model for Peak Current Mode Control
- Small Signal Model for Frequency Compensation
- APPLICATION INFORMATION
- Design Guide — Step-By-Step Design Procedure
- Selecting the Switching Frequency
- Output Inductor Selection (LO)
- Output Capacitor
- Catch Diode
- Input Capacitor
- Slow Start Capacitor
- Bootstrap Capacitor Selection
- Under Voltage Lock Out Set Point
- Output Voltage and Feedback Resistors Selection
- Compensation
- Discontinuous Mode and Eco Mode Boundary
- APPLICATION CURVES
- Power Dissipation Estimate
- Layout
- Revision History

TPS54060
SLVS919A –JANUARY 2009–REVISED JULY 2010
www.ti.com
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54060 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the level set by the
COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output
current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. The Eco-Mode™ is implemented with a minimum clamp on the COMP pin.
Slope Compensation Output Current
The TPS54060 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
Pulse Skip Eco-Mode
The TPS54060 operates in a pulse skip Eco mode at light load currents to improve efficiency by reducing
switching and gate drive losses. The TPS54060 is designed so that if the output voltage is within regulation and
the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the
device enters Eco mode. This current threshold is the current level corresponding to a nominal COMP voltage or
500mV.
When in Eco-mode, the COMP pin voltage is clamped at 500mV and the high side MOSFET is inhibited. Further
decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level.
Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates
for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high side MOSFET is enabled
and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The
output voltage re-charges the regulated value (see Figure 25), then the peak switch current starts to decrease,
and eventually falls below the Eco mode threshold at which time the device again enters Eco mode.
For Eco mode operation, the TPS54060 senses peak current, not average or load current, so the load current
where the device enters Eco mode is dependent on the output inductor value. For example, the circuit in
Figure 50 enters Eco mode at about 20 mA of output current. When the load current is low and the output
voltage is within regulation, the device enters a sleep mode and draws only 116mA input quiescent current. The
internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip
mode, the switching transitions occur synchronously with the external clock signal.
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