TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 0.5A, 42V STEP DOWN DC/DC CONVERTER WITH ECO-MODE™ Check for Samples: TPS54040 FEATURES 1 • • • 2 • • • • • • • 3.5V to 42V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads with a Pulse Skipping Eco-mode™ 116μA Operating Quiescent Current 1.3μA Shutdown Current 100kHz to 2.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 PACKAGE DISSIPATION RATINGS (1) (1) PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT MSOP 57 °C/W Test board conditions: A. 3 inches × 3 inches, 2 layers, thickness: 0.062 inch B. 2-ounce copper traces located on the top and bottom of the PCB C. 6 (13 mil diameters) THERMAL VIAS LOCATED UNDER THE DEVICE PACKAGE ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 3.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2500 kHz 720 kHz 2200 kHz TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching Frequency Range using RT mode fSW Switching frequency 100 RT = 200 kΩ 450 Switching Frequency Range using CLK mode 581 300 Minimum CLK input pulse width 40 RT/CLK high threshold 1.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DEVICE INFORMATION PIN CONFIGURATION MSOP10 (TOP VIEW) BOOT 1 VIN 2 10 Thermal Pad (11) PH 9 GND 8 COMP EN 3 SS/TR 4 7 VSENSE RT/CLK 5 6 PWRGD PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 500 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 Figure 1.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 150 40 VI = 12 V VI = 12 V 130 110 gm - mA/V gm - mA/V 30 90 20 70 10 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 50 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 120 100 VI = 12 V VI = 12 V, TJ = 25°C 80 % of Nominal fsw II(SS/TR) - mA 115 110 60 40 105 20 100 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 0 SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin) 2 TJ = 25°C I(VIN) - mA 1.5 1 0.5 1 0.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE PWRGD THRESHOLD vs JUNCTION TEMPERATURE 115 100 VI = 12 V PWRGD Threshold - % of Vref VI = 12 V RDSON - W 80 60 40 20 0 -50 VSENSE Rising 110 VSENSE Falling 105 100 VSENSE Rising 95 VSENSE Falling 90 -25 0 50 25 75 100 125 85 -50 150 -25 0 125 150 Figure 20.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 OVERVIEW The TPS54040 device is a 42-V, 0.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS54040 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) VOUT(ac) IL PH Figure 25. Pulse Skip Mode Operation Low Dropout Operation and Bootstrap Voltage (BOOT) The TPS54040 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high side MOSFET is off and the low side diode conducts.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) voltage is greater than 2.1V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Enable and Adjusting Undervoltage Lockout The TPS54040 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 28 to adjust the input voltage UVLO by using the two external resistors.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) R2 = VENA VSTART - VENA V + I1 - ENA R1 R3 (5) Slow Start/Tracking Pin (SS/TR) The TPS54040 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 31 using two TPS54040 devices.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Figure 33 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the pull up current source must be doubled in Equation 6. Figure 34 shows the results of Figure 33. TPS54040 EN VOUT 1 SS/TR PWRGD TPS54040 VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 35.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) deltaV = Vout1 - Vout2 R1 > 2800 ´ Vout1 - 180 ´ deltaV (9) (10) EN EN VOUT1 VOUT1 VOUT2 Figure 36. Ratio-metric Startup with Tracking Resistors VOUT2 Figure 37. Ratiometric Startup with Tracking Resistors EN VOUT1 VOUT2 Figure 38.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54040 is adjustable over a wide range from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 42. The square wave amplitude must transition lower than 0.5V and higher than 2.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) PH PH EXT EXT IL IL Figure 43. Plot of Synchronizing in ccm Figure 44. Plot of Synchronizing in dcm PH EXT IL Figure 45.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor between the values of 10 and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) PH VO Power Stage gmps 1.9 A/V a b RESR R1 RL COMP c 0.8 V R3 CO C2 RO VSENSE COUT gmea 97 mA/V R2 C1 Figure 46. Small Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 47 describes a simple small signal model that can be used to understand how to design the frequency compensation.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) VO Adc VC RESR fp RL gmps COUT fz Figure 47.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C2 C1 R3 C2 C1 Figure 48. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 49.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Z1 = 1 2p ´ R3 ´ C1 P2 = (24) 1 2p ´ R3 | | RO ´ (C2 + CO ) type 2a (25) 1 P2 = type 2b 2p ´ R3 | | RO ´ CO P2 = (26) 1 type 1 2 p ´ R O ´ (C2 + C O ) (27) APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 Figure 50. High Frequency, 5V Output Power Supply Design with Adjusted UVLO. Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 IL(rms) = (IO ) 2 www.ti.com 1 æ VOUT ´ (Vinmax - VOUT ) ö + ´ç ÷ ÷ 12 çè Vinmax ´ LO ´ fSW ø 2 Iripple ILpeak = Iout + 2 (30) (31) Output Capacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in load current.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current the output capacitor needs to support.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com Input Capacitor The TPS54040 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the 47μF output capacitor up to 5.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 ¦ z mod = www.ti.com 1 2 ´ p ´ Resr × Cout (42) fco = f p mod ´ f z mod (43) fco = f f p mod ´ sw 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 1.9A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5V, 0.8V and 92μA/V, respectively. R4 is calculated to be 77.1 kΩ, use the nearest standard value of 76.8kΩ.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 Figure 53. Output Ripple CCM Figure 54. Output Ripple, DCM Figure 55. Output Ripple, PSM Figure 56. Input Ripple CCM 100 90 80 VIN = 24 V Efficiency - % 70 VIN = 15 V VIN = 12 V VIN = 34 V 60 VIN = 42 50 40 30 20 10 VOUT = 5.0 V 0 0 Figure 57. Input Ripple DCM 0.05 0.10 0.15 0.20 0.25 0.30 0.35 IO - Output Current - A 0.40 0.45 0.50 Figure 58.
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com 100 60 180 40 120 150 90 80 Phase 90 70 Vin = 12 V Vin = 15 V Vin = 34 V 50 30 Gain - dB Efficiency - % 20 60 Vin = 24 V Vin = 42 V 40 Gain 0 0 -30 -60 -20 30 Phase - o 60 -90 20 -40 -120 -60 -180 VOUT = 5.0 V 10 0 0 0.02 0.04 0.06 IO - Output Current - A -150 0.10 0.08 Figure 59. Light Load Efficiency IO = 0.2 A 0.06 0.04 0.04 Regulation (%) Regulation (%) 1-106 0.08 VI = 24 V 0.02 0 -0.02 0.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 Power Dissipation Estimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
TPS54040 SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
TPS54040 www.ti.com SLVS918A – MARCH 2009 – REVISED SEPTEMBER 2013 Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 50 is 0.55 in2. This area does not include test points or connectors. VIN + CIN Cboot Lo BOOT VIN PH GND R1 Cd + Co GND R2 VOUT VSENSE EN SS/TR COMP Rcomp RT/CLK Css Cpole RT Czero Figure 64.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54040DGQR Package Package Pins Type Drawing MSOPPower PAD DGQ 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54040DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.
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