Datasheet

( ) ( )
2
2
IN(max) OUT OUT FD J SW IN(max) FD
D
IN(max)
V V I V C f V V
P
V
- ´ ´ ´ ´ +
= +
OUT OUT
SS
SSAVG
C V 0.8
t
I
´ ´
>
OUT
Pmod
OUT OUT
I
f
2 V Cp
=
´ ´
TPS5401
SLVSAB0 –DECEMBER 2010 www.ti.com
The B160A has a junction capacitance (C
J
) of 110 pF. Using Equation 24, the selected diode dissipates 0.29 W.
This power dissipation, depending on mounting techniques, should produce a 5.9°C temperature rise in the diode
when the input voltage is 42 V and the load current is 0.5 A.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
(24)
Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage-slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS5401 reach the current limit, or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage-slew rate solves both of these problems.
The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 25 can be used to find the minimum slow-start time, t
SS
,
necessary to charge the output capacitor, C
OUT
, from 10% to 90% of the output voltage, V
OUT
, with an average
slow-start current of I
SSAVG
. In the example, to charge the 220 mF output capacitor up to 5 V while only allowing
the average input current I
SSAVG
to be 0.2 A would require a 4.4-ms slow-start time.
(25)
Once the slow-start time is known, the slow-start capacitor value can be calculated using Equation 4. For the
example circuit, the slow-start time is set to a value of 3.2 ms, which requires a 0.01-µF capacitor.
Bootstrap Capacitor Selection
A 0.1-mF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V
or higher voltage rating.
Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS5401. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. The supply should turn on and start switching once the
input voltage increases above power-up threshold (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below the power-down threshold (UVLO stop).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example
application, because the minimum input voltage is 7.5 V, when the maximum input voltage is 35 V, the voltage at
the EN pin exceeds the absolute voltage rating of the EN pin. So the UVLO is not set externally in this design.
Compensation
The external compensation used with the TPS5401 allows for a wide range of output filter configurations. A large
range of capacitor values and types of dielectric is supported. This design example uses an aluminum electrolytic
output capacitor. A design example with the ceramic dielectric output capacitors can be found in the TPS54040
data sheet (SLVS918). More accurate designs can be found in the SwitcherPro software.
The peak-current mode PWM modulator and the output filter generate a pair of power stage pole and zero which
are determined using Equation 26 and Equation 27.
(26)
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