Datasheet

10
20 30
40
2500
2000
1500
1000
500
0
f – Switching Frequency – kHz
SW
V – Input Voltage – V
IN
V = 5 V
OUT
Shift
Skip
TPS5401
Clock
Source
PLL
R
T
RT/CLK
TPS5401
www.ti.com SLVSAB0 –DECEMBER 2010
DETAILED DESCRIPTION (continued)
I
L
Inductor current
R
dc
Inductor resistance
V
IN
Maximum input voltage
V
OUT
Output voltage
V
OUTSC
Output voltage during short
V
d
Diode voltage drop
r
DS(on)
Switch on resistance
t
ON
Controllable on-time
ƒ
DIV
Frequency divide equals (1, 2, 4, or 8)
Figure 38. Maximum Switching Frequency vs. Input Voltage
How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin as shown in Figure 39. The square-wave
amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time greater
than 40 ns and an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The
rising edge of the PH signal is synchronized to the falling edge of the RT/CLK pin signal.
Figure 39. Synchronizing to a System Clock
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