Datasheet

TPS5401

SLVSAB0 –DECEMBER 2010

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DETAILED DESCRIPTION

Fixed Frequency PWM Control

The TPS5401 uses an adjustable fixed-frequency, peak current mode control. The output voltage is compared

through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives

the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output

is compared to the high-side power-switch current. When the power-switch current reaches the level set by the

COMP voltage, the power switch is turned off. The COMP pin voltage increases and decreases as the output

current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a

maximum level. The Eco-mode control scheme is implemented with a minimum clamp on the COMP pin.

Slope Compensation Output Current

The TPS5401 adds a compensating ramp to the switch current signal. This slope compensation prevents

sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range.

Pulse-Skip Eco-mode Control Scheme

The TPS5401 operates in a pulse-skip Eco-mode control scheme at light load currents to improve efficiency by

reducing switching and gate-drive losses. The TPS5401 is designed so that if the output voltage is within

regulation and the peak switch current at the end of any switching cycle is below the pulse-skipping current

threshold, the device enters the Eco-mode control scheme. This current threshold is the current level

corresponding to a nominal COMP voltage of 500 mV.

When in the Eco-mode control scheme, the COMP pin voltage is clamped at 500 mV, and the high-side

MOSFET is inhibited. Further decreases in load current or increases in output voltage cannot drive the COMP

pin below this clamp voltage level.

Because the device is not switching, the output voltage begins to decay. As the voltage control loop

compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side

MOSFET is enabled, and a switching pulse initiates on the next switching cycle. The peak current is set by the

COMP pin voltage. The output voltage recharges the regulated value (see Figure 25); then the peak switch

current starts to decrease and eventually falls below the Eco-mode control-scheme threshold, at which time the

device again enters the Eco-mode control scheme.

For Eco-mode control-scheme operation, the TPS5401 senses peak current, not average or load current, so the

load current where the device enters the Eco-mode control scheme is dependent on the output inductor value.

For example, the circuit in Figure 40 enters the Eco-mode control scheme at about 20 mA of output current.

When the load current is low and the output voltage is within regulation, the device enters a sleep mode and

draws only 116 mA of input quiescent current. The internal PLL remains operating when in sleep mode. When

operating at light load currents in the pulse-skip mode, the switching transitions occur synchronously with the

external clock signal.

Product Folder Link(s): TPS5401