Datasheet

Layout
3-2
3.1 Layout
The board layout for the TPS54010EVM-067 is shown in Figure 3−1 through
NO TAG. The top−side layer of the TPS54010EVM-067 is laid out in a manner
typical of a user application. The top, bottom, and internal ground layers are
2.0-oz. copper.
The top layer contains the main power traces for Vin, Vout, and Vphase. Also
on the top layer are connections for the remaining pins of the TPS54010 and
a large area filled with ground. The bottom layer contains ground and Vout
copper areas, and some signal routing. The two internal layers are dedicated
ground layers. The top and bottom and internal ground traces are connected
with multiple vias placed around the board including 10 directly under the
TPS54010 device to provide a thermal path from the PowerPAD land to
ground.
The input decoupling capacitors (C1, C9, C10, and C11), bias decoupling
capacitor (C4), and bootstrap capacitor (C3) are all located as close to the IC
as possible. In addition, the compensation components are also located close
to the IC. The compensation circuit ties to the output voltage at the point of
regulation, adjacent to the high-frequency bypass output capacitor.
Figure 3−1. Top−Side Layout