E ! User’s Guide August 2004 PMP Systems Power SLVU114
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage ranges of 2.2 V to 4 V (PVIN) and 3 V to 4 V (VIN), and output voltage ranges of 0.9 V (Vout min) to 2.5 V (Vout max, with PVIN >3.3 V). Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 3−1 3−2 3−3 3−4 3−5 4−1 Measured Efficiency, TPS54010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 This chapter contains introductory information for the TPS54010 and support documentation for the TPS54010EVM-067 evaluation module (HPA067). Included in this user’s guide are the performance specifications, the schematic, and the bill of materials for the TPS54010EVM-067. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . .
Background 1.1 Background The TPS54010 dc/dc converter is designed to provide up to a 14-A output from an input voltage source of 2.2 V to 4 V. Rated input voltage and output current range are given in Table 1−1. This evaluation module is designed to demonstrate the small PCB areas that may be achieved when designing with the TPS54010 regulator and does not reflect the high efficiencies that may be achieved when designing with this part.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54010EVM-067 performance specifications is provided in Table 1−2. Specifications are given for an input voltage of PVIN = VIN = 3.3 V and an output voltage of 1.5 V, unless otherwise specified. The TPS54010EVM-067 is designed and tested for PVIN = 2.2 V to 3.5 V. Above 3.5 V, the EVM still operates; however, the phase margin is less than 45 degrees.
Modifications 1.3 Modifications Whereas the TPS54010EVM−067 is designed to demonstrate the small size that can be attained when designing with the TPS54010, many of the features, which allow for extensive modifications, have been included in this EVM. 1.3.1 Output Voltage Set Point To change the output voltage of the EVM, it is necessary to change the value of resistor R2. Changing the value of R2 can change the output voltage in the range of 0.9 V to 2.5 V.
Modifications 1.3.3 Input Filter An onboard electrolytic input capacitor is included at C1. Depending on the application, this capacitor can be removed. 1.3.4 Split Input Voltage Rails The TPS54010 is provided with two input voltage rails, PVIN and VIN. In normal operation, the two input voltages would be applied per Table 1−1 at the J1 and J2 connectors. It is possible to operate the EVM from a single 3−V to 3.5−V source by applying the voltage at the J1 connector and installing a jumper on JP1. 1.3.
Trademarks 1.4 Trademarks Swift and PowerPAD are trademarks of Texas Instruments.
Chapter 2 This chapter describes how to properly connect, set up, and use the TPS54010EVM-067 evaluation module. The chapter also includes typical test results for the TPS54010EVM-067 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54010EVM-067 is provided with input/output connectors and test points as shown in Table 2−1. Connect a power supply capable of supplying 12 A to J1 through a pair of 14 AWG wires. Connect a power supply capable of supplying 25 mA to J2 through a pair of 22 AWG wires. Connect the load to J3 through a pair of 14 AWG wires. The maximum load current capability is 14 A. Minimize wire lengths to reduce losses in the wires.
Efficiency 2.2 Efficiency The TPS54010EVM-067 efficiency peaks at load current of about 2 A and then decreases as the load current increases towards full load. Figure 2−1 shows the efficiency for the TPS54010 at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs. The efficiency is slightly lower at 700 kHz than at lower switching frequencies due to the gate and switching losses in the MOSFETs.
Output Voltage Regulation 2.3 Output Voltage Regulation The output voltage load regulation of the TPS54010EVM-067 is shown in Figure 2−2, whereas, the output voltage line regulation is shown in Figure 2−3. Measurements are given for an ambient temperature of 25°C. Figure 2−2. Load Regulation Output Voltage Change vs. Output Current 0.5 0.4 Output Voltage Variation − % 0.3 0.2 0.1 0 −0.1 −0.2 PVIN=2.2V −0.3 PVIN=2.5V −0.4 PVIN=3.3V −0.5 0 3 6 9 12 15 I out − A Figure 2−3.
Load Transients 2.4 Load Transients The TPS54010EVM-067 response to load transients is shown in Figure 2−4. The current step is from 25 to 75 percent of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2−4.
Loop Characteristics 2.5 Loop Characteristics The TPS54010EVM-067 loop response characteristics are shown in Figure 2−5 and Figure 2−6. Gain and phase plots are shown for each device at PVIN voltages of 2.2 V and 3.5 V. Figure 2−5. Measured Loop Response, TPS54010, PVIN = 2.
Loop Characteristics Figure 2−6. Measured Loop Response, TPS54010, VIN = 3.
Output Voltage Ripple 2.6 Output Voltage Ripple The TPS54010EVM−067 output voltage ripple is shown in Figure 2−7. The input voltages are PVIN = 2.5 V and VIN = 3.3 V for the TPS54010. Output current is the rated full load of 14 A. Voltage is measured directly across output capacitors. Figure 2−7.
Input Voltage Ripple 2.7 Input Voltage Ripple The TPS54010EVM−067 output voltage ripple is shown in Figure 2−8. The input voltages PVIN = 2.5 V and VIN = 3.3 V for the TPS54010. Output current for each device is rated full load of 14 A. Figure 2−8. Input Voltage Ripple, TPS54010 VI (RIPPLE) = 100 mV/div (ac Coupled) V(PH) = 1 V/div t − Time = 500 ns/div 2.8 Powering Up and Down The TPS54010EVM-067 start-up waveforms are shown in Figure 2−9 and Figure 2−10.
Powering Up and Down Figure 2−9. Power Up, VOUT Relative to VIN VIN= 1 V/div VOUT = 1 V/div t − Time = 5 ms/div Figure 2−10.
Chapter 3 This chapter provides a description of the TPS54010EVM−067 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54010EVM-067 is shown in Figure 3−1 through NO TAG. The top−side layer of the TPS54010EVM-067 is laid out in a manner typical of a user application. The top, bottom, and internal ground layers are 2.0-oz. copper. The top layer contains the main power traces for Vin, Vout, and Vphase. Also on the top layer are connections for the remaining pins of the TPS54010 and a large area filled with ground.
Layout Figure 3−2. Internal Ground Layer 2 Figure 3−3.
Figure 3−4. Bottom−Side Layout (Looking From Top Side) Figure 3−5.
Chapter 4 This chapter presents the TPS54010EVM−067 schematic and bill of materials. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic The schematic for the TPS54010EVM−067 is shown in Figure 4−1. Figure 4−1.
Bill of Materials 4.2 Bill of Materials Table 4−1 contains the bill of materials for the TPS54010EVM−067. Table 4−1. TPS54010EVM-067 Bill of Materials Count RefDes Description Size MFR Part Number 1 C1 Capacitor, POSCAP, 330-µF, 6.3−V, 10 µW, 20% E Sanyo 6TPD330M 1 C13 Capacitor, ceramic, 0.1-µF, 16−V, X7R, 10% 603 std std 1 C2 Capacitor, ceramic, 100-µF 6.3−V, X5R, 20% 1210 TDK C3225X5R0J107M − C12 Capacitor, ceramic, 100-µF, 6.
4-4
