Datasheet

TPS53315
www.ti.com SLUSAE6 –DECEMBER 2010
PIN FUNCTIONS (continued)
PIN
I/O/P
(1)
DESCRIPTION
NAME NO.
Open drain power good flag. Provides a 1-ms start up delay after the VFB pin voltage falls within
PGOOD 32 O specified limits. When the VFB pin voltage goes outside the specified limits, the PGOOD pin goes low
within 10 µs.
2
5
6
PGND 7 G Power GND
8
9
10
Switching frequency selection. Connect a resistance to GND or VREG to select switching frequency using
RF 38 I
Table 2. The switching frequency is detected and stored during the startup.
OCL detection threshold setting pin. 10 µA at room temperature, 4700 ppm/°C current is sourced and set
the OCL trip voltage as follows.
TRIP 35 I
space V
OCL
= V
TRIP
/8 ( V
TRIP
≤1.2 V, V
OCL
≤ 150 mV)
Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL-node.
VBST 30 P
Internally connected to the VREG pin via bootstrap MOSFET switch.
VDD 40 P Controller power supply input.
VFB 37 I Output feedback input. Connect this pin to V
OUT
through a resistor divider.
11
12
VIN 13 P Conversion power input.
14
15
VREG 3 P 5-V LDO output.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS53315