Datasheet

-
= ´
´
IN OUT
INJ _ SW
SW
V V
D
V
R7 C1 f
( )
( )
= ´ +
´ ´
IND ripple
INJ _ OUT
IND ripple
OUT SW
I
V ESR I
8 C f
+
= +
INJ _ SW INJ _ OUT
VFB
V V
V 0.6
2
-
= ´
OUT FB
FB
V V
R1 R2
V
TPS53315
www.ti.com SLUSAE6 –DECEMBER 2010
External Parts Selection with All Ceramic Output Capacitors
When ceramic output capacitors are used, the stability criteria in Equation 2 cannot be satisfied. The ripple
injection approach as shown in Equation 10 is implemented to increase the ripple on the VFB pin and make the
system stable. C2 can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF.
The increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the
VFB pin has two components, one coupled from SW node and the other coupled from V
OUT
and they can be
calculated using Equation 10 and Equation 11.
(10)
(11)
The DC value of VFB can be calculated by Equation 12:
(12)
And the resistor divider value can be determined by Equation 13:
(13)
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a layout work using the TPS53315.
• The power components (including input/output capacitors, inductor and TPS53315) should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed
away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground
plane(s) and shield feedback trace from power traces and components.
• Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC
current loop.
• Since the TPS53315 controls output voltage referring to voltage across the V
OUT
capacitor, the top-side
resistor of the voltage divider should be connected to the positive node of VOUT capacitor. In a same manner
both bottom side resistor and GND pad of the device should be connected to the negative node of V
OUT
capacitor. The trace from these resistors to the VFB pin should be short and thin. Place on the component
side and avoid via(s) between these resistors and the device.
• Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
• Connect the frequency setting resistor from RF pin to ground, or to the VREG pin, and make the connections
as close as possible to the device. The trace from the RF pin to the resistor and from the resistor to ground
should avoid coupling to a high-voltage switching node.
• Connect the MODE setting resistor from MODE pin to ground, or to the PGOOD pin, and make the
connections as close as possible to the device. The trace from the MODE pin to the resistor and from the
resistor to ground should avoid coupling to a high-voltage switching node.
• The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,
should be as short and wide as possible.
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Product Folder Link(s): TPS53315