Datasheet

R1
R2
Voltage
Divider
37
+
VFB
+
0.6 V
PWM
Control
Logic
and
Divider
VIN
L
ESR
C
OUT
V
C
R
LOAD
I
IND
I
OUT
UDG-10203
I
C
Switching Modulator
Output
Capacitor
V
OUT
TPS53315
LL
VIN
( )
=
´ ´
OUT
1
H s
s ESR C
= £
p´ ´
SW
0
OUT
f
1
f
2 ESR C 4
TPS53315
www.ti.com SLUSAE6 –DECEMBER 2010
Small Signal Model
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 37.
Figure 37. Simplified Modulator Model
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).
The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on-cycle substantially
constant.
(1)
For the loop stability, the 0 dB frequency, ƒ
0
, defined in Equation 2 must be lower than ¼ of the switching
frequency.
(2)
According to Equation 2, the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor
chemistry. For example, specialty polymer capacitors (SP-CAP) have C
OUT
on the order of several 100 µF and
ESR in range of 10 mΩ. These makes ƒ
0
on the order of 100 kHz or less and the loop is stable. However,
ceramic capacitors have an ƒ
0
at more than 700 kHz, and need special care when used with this modulator. An
application circuit using ceramic capacitors is described in External Parts Selection section under All Ceramic
Output Capacitors.
Ramp Signal
The TPS53315 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. The feedback
voltage is compared with the reference information to keep the output voltage in regulation. By adding a small
ramp signal to the reference, the signal-to-noise ratio at the onset of a new switching cycle is improved.
Therefore the operation becomes less jittery and more stable. The ramp signal is controlled to start with –7 mV at
the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in steady state.
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