Datasheet

TPS53313
FB
COMP
PGND
PGND
MODE/SS
BP3
AGND
RT/SYNC
PGND
PGND
PGND
PGND
SW
VIN
VIN VIN
VIN
PG
EN
SW SW SW
BP7
VBST
2
3
4
5
6
7
8
9
10
11
1
12
1314
1516
17
18
24
23
22
21
19
20
Exposed Pad
TPS53313
SLUSAS8 –DECEMBER 2011 www.ti.com
DEVICE INFORMATION
RGE (QFN) PACKAGE
24 PINS
(BOTTOM VIEW)
PIN DESCRIPTIONS
PIN
I/O
(1)
DESCRIPTION
NAME NO.
AGND 20 G Device analog ground terminal
BP3 19 P Input bias supply for analog functions
BP7 18 P Bias for internal circuitry and driver
COMP 23 O Error amplifier compensation terminal. Type III compensation method is generally recommended for stability.
EN 1 I Enable pin.
FB 24 I Voltage feedback pin. Use for OVP, UVP and power good determination
PG 2 O Power good output flag. Open drain output. Pull up to an external rail via a resistor
7
8
9
PGND P Device power ground terminal
10
11
12
Mode configuration pin. Connect with a resistor to GND sets different modes and soft-start time, parallel a
capacitor (or no capacitor) with the resistor changes the current limit threshold. See Table 1 and Table 2 for
MODE/SS 22 I
resistor and capacitor settings. (shorting MODE/SS pin to supply inhibits the device. Shorting MODE/SS pin
to AGND is equivalent to 10-kΩ resistor setting—not recommended)
RT/SYNC 21 I/O Synchronized to external clock. Program the switching frequency by connecting with a resistor to GND.
13
14
SW O Output inductor connection to integrated power devices
15
16
VBST 4 P Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal
3
4
VIN P Gate driver supply and power conversion voltage.
5
6
(1) I – Input; B – Bidirectional; O – Output; G – Ground; P – Supply (or Ground)
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