Datasheet

R3
R1
C1
R2
R4
C2
C3
+
COMP
VREF
UGD-11238
UDG-11237
Frequency
f
Z1
f
Z2
f
P2
f
P3
Gain (dB)
P1
f 0=
P2
1
f
2 R3 C1
=
´ p ´ ´
P3
1 1
f
C2 C3
2 R4 C3
2 R4
C2 C3
= @
´
´ p ´ ´
æ ö
´ p ´ ´
ç ÷
+
è ø
TPS53313
SLUSAS8 –DECEMBER 2011 www.ti.com
Figure 15. Type III Compensation Network Figure 16. Type III Compensation Network
Schematic Waveform
(18)
(19)
(20)
The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One
pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to
attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a
compromise between high phase margin and fast response. A phase margin higher than 45° is required for
stable operation.
For DCM operation, a capacitor with a value between 100 pF and 220 pF is recommended for C3 when the
output capacitance is between 22 µF and 220 µF.
LAYOUT CONSIDERATIONS
Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout:
• Separate the power ground and analog ground planes. Connect them together at one location.
• Use 4 vias to connect the thermal pad to power ground.
• Place VIN, BP7 and BP3 decoupling capacitors as close to the device as possible.
• Use wide traces for VIN, PGND and SW. These nodes carry high-current and also serve as heat sinks.
• Place feedback and compensation components as close to the device as possible.
• Keep analog signals (FB, COMP) away from noisy signals (SW, VBST).
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