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User's Guide

SLUU428A–July 2010–Revised November 2010

Using the TPS53311EVM-561, a 3-A Eco-mode™

Integrated Switcher With Master-Slave

The TPS53311EVM-561 evaluation module (EVM) is a high-efficiency evaluation platform with two

TPS53311 3-A integrated FET step-down converters working in a Master-Slave synchronization scheme.

The two outputs are 1.5 V/3 A (master) and 1.2 V/3 A (slave) from a 3.3-V or 5-V input bus. The EVM

uses the TPS53311 synchronous buck controller with integrated switcher.

spacer - to push the title: List of Figures to page 2

Contents

1 Description ................................................................................................................... 3

1.1 Typical Applications ................................................................................................ 3

1.2 Features ............................................................................................................. 3

2 Electrical Performance Specifications .................................................................................... 4

3 Schematic .................................................................................................................... 5

4 Test Setup ................................................................................................................... 6

4.1 Test Equipment ..................................................................................................... 6

4.2 Recommended Test Setup ....................................................................................... 7

5 Configuration ................................................................................................................ 7

5.1 5-Vin Option (J1: 5-Vin Option) .................................................................................. 7

5.2 Master Mode Selection (J2: MST Mode) ....................................................................... 8

5.3 Slave Mode Selection (J7: SLV Mode) .......................................................................... 8

5.4 Synchronization (J5: SYNC) ...................................................................................... 8

5.5 Master Enable (J4: EN_MST) .................................................................................... 8

5.6 Slave Enable (J9: EN_SLV) ...................................................................................... 9

6 Test Procedure .............................................................................................................. 9

6.1 Line/Load Regulation and Efficiency Measurement Procedure .............................................. 9

6.2 Loop Gain/Phase Measurement ................................................................................. 9

6.3 List of Test Points .................................................................................................. 9

6.4 Equipment Shutdown ............................................................................................ 10

7 Performance Data and Typical Characteristic Curves ................................................................ 10

7.1 Efficiency .......................................................................................................... 11

7.2 Load Regulation .................................................................................................. 11

7.3 Line Regulation ................................................................................................... 12

7.4 1.5-V Output Ripple .............................................................................................. 12

7.5 1.5-V Switching Node at Full Load ............................................................................. 13

7.6 1.5-V Switching Node at No Load .............................................................................. 13

7.7 Master-Slave 180° Synchronization ............................................................................ 14

7.8 1.5-V Master Turnoff During Master-Slave Synchronization ................................................ 14

7.9 1.5-V Output Transient ........................................................................................... 15

7.10 1.5-V Turnon Waveform ......................................................................................... 15

7.11 1.5-V Turnoff Waveform ......................................................................................... 16

7.12 1.5-V Bode Plot ................................................................................................... 16

7.13 EVM Top Board Thermal Image ................................................................................ 17

8 EVM Assembly Drawings and PCB Layout ............................................................................ 17

9 Bill of Materials ............................................................................................................. 21

SLUU428A–July 2010–Revised November 2010 Using the TPS53311EVM-561, a 3-A Eco-mode™ Integrated Switcher With

Master-Slave

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Summary of content (23 pages)

PAGE 1
User's Guide SLUU428A – July 2010 – Revised November 2010 Using the TPS53311EVM-561, a 3-A Eco-mode™ Integrated Switcher With Master-Slave The TPS53311EVM-561 evaluation module (EVM) is a high-efficiency evaluation platform with two TPS53311 3-A integrated FET step-down converters working in a Master-Slave synchronization scheme. The two outputs are 1.5 V/3 A (master) and 1.2 V/3 A (slave) from a 3.3-V or 5-V input bus. The EVM uses the TPS53311 synchronous buck controller with integrated switcher.
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www.ti.com List of Figures 1 TPS53311EVM-561 Schematic ........................................................................................... 5 2 Tip and Barrel Measurement for Vout Ripple 6 3 TPS53311EVM-561 Recommended Test Setup 7 4 5 6 7 8 9 10 ........................................................................... ....................................................................... TPS53311EVM-561 Efficiency .........................................................................
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Description www.ti.com 1 Description The TPS53311EVM-561 is designed to use a regulated 3.3-V or 5-V bus to produce outputs at up to 3 A of load current. The output is 1.5-V master and 1.2-V slave. The TPS53311EVM-561 is designed to demonstrate the TPS53311 in a typical low-voltage application while providing a number of test points to evaluate the performance of the TPS53311. 1.1 Typical Applications • • • • • • 1.
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Electrical Performance Specifications 2 www.ti.com Electrical Performance Specifications Table 1. TPS53311EVM-561 Electrical Performance Specifications (1) PARAMETER TEST CONDITIONS MIN TYP 2.9 3.3/5 MAX UNITS INPUT CHARACTERISTICS VIN Input Voltage range* Vin Maximum input current Vin = 3.3 V,1.5 V/3 A, 1.2 V/3 A, FCCM No load input current Vin=3.3 V, 1.5 V/0 A, 1.2 V/0 A, FCCM 6 2.82 40 V A mA OUTPUT CHARACTERISTICS Master Output voltage Vo_MST 1.485 1.5 1.
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Not used SLUU428A – July 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Enable 1 . Jumper shorts on J4 and J 9 : Disable the converter (Default setting) 2 . No Jumper shorts on J4 and J 9 : Enable the converter Mode Configuration : See datasheet for detail SYNC option 1 . Jumper shorts on J5 : Master and slave are synchronized(Default setting) 2 . No Jumper shorts on J5 : Master and slave are not synchronized 3 5 Vin option 1 .
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Test Setup 4 Test Setup 4.1 Test Equipment www.ti.com Voltage Source VIN: The input voltage source VIN must be a 0-V to 6-V variable dc source capable of supplying 3 Adc. Connect Vin to J6 as shown in Figure 3. Multimeters: V1: Vin at TP5 (Vin_MST) and TP8 (GND) V2: 1.5 Vout at TP7 (Vout_MST) and TP10 (GND) V3: 1.2 Vout at TP19 (Vout_SLV) and TP21 (GND) A1: Vin input current Output Load: Load1: The output load1 must be an electronic constant resistance mode load capable of 0 Adc to 5 Adc at 1.5 V.
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Configuration www.ti.com 4.2 Recommended Test Setup + V1 V2 DC Load1 TEXAS INSTRUMENTS Source VIN A1 + V3 Load2 Figure 3. TPS53311EVM-561 Recommended Test Setup Figure 3 is the recommended test setup to evaluate the TPS53311EVM-561. Working at an ESD workstation, ensure that any wrist straps, bootstraps, or mats are connected referencing the user to earth ground before handling the EVM. Input Connections: 1.
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Configuration www.ti.com Table 2. 5-Vin Option 5.2 Jumper set to Input Voltage 1-2 pin shorted 3.3 Vin 2-3 pin shorted 5 Vin Master Mode Selection (J2: MST Mode) The Master mode selection can be set by J2. Default setting: FCCM_Mst Table 3. Master Mode Selection 5.
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Test Procedure www.ti.com Table 6. Master Enable Selection 5.6 Jumper set to Enable/Disable Controller Jumper shorts on J4 Disable 1.5-V Master output No Jumper on J4 Enable 1.5-V Master output Slave Enable (J9: EN_SLV) The Slave Enable can be set by J9. Default setting: Jumper on J9, Table 7. Slave Enable Selection Jumper set to Enable/Disable Controller Jumper shorts on J9 Disable 1.2-V Master output No Jumper on J9 Enable 1.2-V Master output 6 Test Procedure 6.
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Performance Data and Typical Characteristic Curves www.ti.com Table 8. Functions of Each Test Points (1) 6.4 Test Points Name Description TP1 (1) CHA_MST Input A for 1.5-V loop injection TP2 CHB_MST Input B for 1.5-V loop injection TP3 3.3VDD 3.3 VDD TP4 GND Ground TP5 Vin_MST Input voltage for 1.5-V master TP6 SW_MST Switching node for 1.5-V master TP7 Vout_MST 1.5-V output TP8 GND Ground TP9 EN_MST Enable for 1.
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Performance Data and Typical Characteristic Curves www.ti.com 7.1 Efficiency 100 3.3 VI,1.5 VO 90 5 VI,1.5 VO 80 3.3 VI,1.2 VO Efficiency - % 70 5 VI,1.2 VO 60 50 40 30 20 10 0 0.001 0.01 0.1 IO - Output Current - A 1 10 NOTE: R-C snubber to reduce switching node ringing has effect on dc-dc converter efficiency. Figure 4. TPS53311EVM-561 Efficiency 7.2 Load Regulation 1.6 1.5 V/1.2 V VO - Output Voltage - V 1.5 3.3Vin, 1.5Vout,FCCM 3.3Vin,1.5Vout, DE 5Vin,1.5Vout, FCCM 5Vin, 1.
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Performance Data and Typical Characteristic Curves 7.3 www.ti.com Line Regulation 1.6 1.5 V/1.2 V VO - Output Voltage - V 1.5 1.5Vout/0A, FCCM 1.5Vout/3A, FCCM 1.5Vout/0A, DE 1.5Vout/3A, DE 1.5Vout/0A, HEF 1.5Vout/3A, HEF 1.2Vout/0A, FCCM 1.2Vout/3A, FCCM 1.2Vout/0A, DE 1.2Vout/3A, DE 1.2Vout/0A, HEF 1.2Vout/3A, HEF 1.4 1.3 1.2 1.1 1 2.9 3.4 3.9 4.4 4.9 VI - Input Voltage - V 5.4 5.9 6.4 Figure 6. TPS53311EVM-561 Line Regulation 7.4 1.
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Performance Data and Typical Characteristic Curves www.ti.com 7.5 1.5-V Switching Node at Full Load TPS53311EVM-561 Test Conditions: 5 Vin, 1.5 V/3 A, FCCM 1.5 Vout Switching Node CH1: SW_MST Figure 8. TPS53311EVM-561 Switching Node at Full Load, 5 Vin, 1.5 V/3 A 7.6 1.5-V Switching Node at No Load TPS53311EVM-561 Test Conditions: 5 Vin, 1.5 V/0 A, FCCM 1.5 Vout Switching Node CH1: SW_MST Figure 9. TPS53311EVM-561 Switching Node at No Load, 5 Vin, 1.
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Performance Data and Typical Characteristic Curves 7.7 www.ti.com Master-Slave 180° Synchronization TPS53311EVM-561 Test Conditions: 3.3 Vin, 1.5 V/3 A, FCCM Master-Slave Synchronization CH1: SW_MST CH2: SW_SLV Figure 10. TPS53311EVM-561 Synchronization 3.3 Vin, 1.5 V/3 A, 1.2 V/3 A 180° Synchronization 7.8 1.5-V Master Turnoff During Master-Slave Synchronization TPS53311EVM-561 Master-Slave Synchronization Test Conditions: 3.3 Vin, 1.5 V/3 A, 1.2 V/3 A FCCM 1.
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Performance Data and Typical Characteristic Curves www.ti.com 7.9 1.5-V Output Transient TPS53311EVM-561 Test Conditions: 5 Vin, 1.5 V/0 A-3 A, FCCM Transient Response CH1: 1.5 Voutput CH2: SW_MST CH3: 1.5 Voutput Current 0 A-3 A Figure 12. TPS53311EVM-561, 1.5-V Output Transient, 5 Vin, 1.5/0 A to 3 A 7.10 1.5-V Turnon Waveform TPS53311EVM-561 Test Conditions: 3.3 Vin, 1.5 V/3 A, FCCM 1.5 Vout Enable Start Up CH1: EN_MST CH2: 1.5 Vout CH3: SW_MST CH4: PG_MST Figure 13.
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Performance Data and Typical Characteristic Curves www.ti.com 7.11 1.5-V Turnoff Waveform TPS53311EVM-561 Test Conditions: 3.3 Vin, 1.5 V/3 A, FCCM 1.5 Vout Enable Turn Off CH1: EN_MST CH2: 1.5 Vout CH3: SW_MST CH4: PG_MST Figure 14. TPS53311EVM-561 Enable Turns Off Waveform, 3.3 Vin, 1.5 V/3 A 7.12 1.5-V Bode Plot Figure 15. TPS53311EVM-561 Bode Plot, 3.3 Vin, 1.
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EVM Assembly Drawings and PCB Layout www.ti.com 7.13 EVM Top Board Thermal Image Figure 16. TPS53311EVM-561 Top Side Thermal Image, 3.3 Vin, 1.5 V/3 A, 1.2 V/3 A 8 EVM Assembly Drawings and PCB Layout Figure 17 through Figure 22) shows the design of the TPS53311EVM-561 printed-circuit board. The EVM has been designed using a 4-layer circuit board with 2-oz copper on outside layers. TEXAS INSTRUMENTS Figure 17.
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EVM Assembly Drawings and PCB Layout www.ti.com Figure 18. TPS53311EVM-561 Bottom Assembly Drawing, Bottom View Figure 19.
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EVM Assembly Drawings and PCB Layout www.ti.com Figure 20. TPS53311EVM-561 Internal Layer 2, Top View Figure 21.
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EVM Assembly Drawings and PCB Layout www.ti.com Figure 22.
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Bill of Materials www.ti.com 9 Bill of Materials The EVM major components list according to the schematic shown in Figure 1 is listed in Table 9. Table 9. Bill of Materials QTY RefDes Description MFR Part Number 4 C1, C2, C15, C16 Capacitor, Ceramic, 2.
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Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.