Datasheet

TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010 www.ti.com
LAYOUT SUGGESTIONS
• Keep the input switching current loop as small as possible.
• Place the input capacitor (C3, C6) close to the top switching FET. The output current loop should also be kept
as small as possible.
• Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin (VFB) of the device.
• Keep analog and non-switching components away from switching components.
• Make a single point connection from the signal ground to power ground.
• Do not allow switching current to flow under the device.
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REVISION HISTORY
Changes from Original (April 2009) to Revision A Page
• Updated the list of Features .................................................................................................................................................. 1
Changes from Revision A (August 2009) to Revision B Page
• Changed Equation 13 From: I
OCL
+ To: I
OCL
- ..................................................................................................................... 17
• Updated Equation 14 by adding minus V
OCLoff
.................................................................................................................... 17
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