Datasheet

TPS51916
DRVL
11
VIN
REFIN GND
V5IN
12
V
OUT
TRIP
MODE
10
7
PGND
VREF
19
18
4
3
VTT
UDG-10197
VTTGND
5
0.22 mF
VTTREF
2
86
10 mF
10 nF
0.1 mF
VTT
VTTGND
VLDOIN
1 mF
#1
#2
#3
PGND
AGND
TPS51916
www.ti.com
SLUSAE1D DECEMBER 2010REVISED JUNE 2012
Layout Considerations
Certain issues must be considered before designing a layout using the TPS51916.
Figure 41. DC/DC Converter Ground System
VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner system GND plane should be inserted, in order to shield and isolate the small signal
traces from noisy power lines.
All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF and TRIP
should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid
coupling. Use internal layer(s) as system GND plane(s) and shield feedback trace from power traces and
components.
The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and
low-side MOSFETs, and back to the negative node of the VIN capacitor(s). Connect the negative node of
the VIN capacitor(s) and the source of the low-side MOSFET as close as possible. (Refer to loop #1 of
Figure 41)
The second important loop is the path from the low-side MOSFET through inductor and VOUT
capacitor(s), and back to source of the low-side MOSFET. Connect the source of the low-side MOSFET
and negative node of VOUT capacitor(s) as close as possible. (Refer to loop #2 of Figure 41)
The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor. To turn off the low-side MOSFET, high current flows from gate of the
low-side MOSFET through the gate driver and PGND pin, and back to source of the low-side MOSFET.
Connect negative node of V5IN capacitor, source of the low-side MOSFET and PGND pin as close as
possible. (Refer to loop #3 of Figure 41)
Connect negative nodes of the VTTREF output capacitor, VREF capacitor and REFIN capacitor and bottom-
side resistance of VREF voltage-divider to GND pin as close as possible. The negative node of the VTT
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 25