Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- VDDQ Switch Mode Power Supply Control
- VREF and REFIN, VDDQ Output Voltage
- Soft-Start and Powergood
- Power State Control
- MODE Pin Configuration
- Discharge Control
- D-CAP™ Mode
- D-CAP2™ Mode Operation
- Light-Load Operation
- VTT and VTTREF
- VDDQ Overvoltage and Undervoltage Protection
- VDDQ Out-of-Bound Operation
- VDDQ Overcurrent Protection
- VTT Overcurrent Protection
- V5IN Undervoltage Lockout Protection
- Thermal Shutdown
- External Components Selection
- Layout Considerations
12
17
16
6
15
14
13
11
V5IN
TPS51916
S3
S5
VREF
VBST
DRVH
SW
DRVL
8
10
REFIN
PGND
7
19
GND
MODE
18 TRIP
20
9
2
3
PGOOD
VDDQSNS
VLDOIN
VTT
1
4
5
VTTSNS
VTTGND
VTTREF
UDG-12075
VDDQ
S5
PGND
5VIN
PGND
VIN
AGND
Powergood
PGND
1 kW
PGND
PGND
0.22 mF
AGND
TPS51916
SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012
www.ti.com
VTT and VTTREF
TPS51916 integrates two high performance, low-drop-out linear regulators, VTT and VTTREF, to provide
complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and
tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-μF (or larger) ceramic capacitor
must be connected close to the VTTREF terminal to ensure stable operation. The VTT responds quickly to track
VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-μF (or
larger) ceramic capacitor(s) need to be connected close to the VTT terminal for stable operation. To achieve tight
regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to
the positive node of VTT output capacitor(s) as a separate trace from the high-current line to the VTT pin.
(Please refer to the Layout Considerations section for details.)
When VTT is not required in the design, following treatment is strongly recommended.
• Connect VLDOIN to VDDQ.
• Tie VTTSNS to VTT, and remove capacitors from VTT to float.
• Connect VTTGND to GND.
• Select MODE2, 3, 4 or 5 shown in Table 2 (Select Non-tracking discharge mode).
• Maintain a 0.22-µF capacitor connected at VTTREF.
• Pull down S3 to GND with 1-kΩ resistance.
Figure 38. Application Circuit When VTT Is Not Required
VDDQ Overvoltage and Undervoltage Protection
The TPS51916 sets the overvoltage protection (OVP) when VDDQSNS voltage reaches a level 20% (typ) higher
than the REFIN voltage. When an OV event is detected, the controller changes the output target voltage to 0 V.
This usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the
low-side MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on, for a minimum on-
time.
After the minimum on-time expires, DRVH is turned off and DRVL is turned on again. This action minimizes the
output node undershoot due to LC resonance. When the VDDQSNS reaches 0 V, the driver output is latched as
DRVH off, DRVL on. VTTREF and VTT are turned off and discharged using the non-tracking discharge
MOSFETs regardless of the tracking mode.
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