Datasheet

700 ms400 ms 1.4 ms
S5
VREF
VDDQ
PGOOD
UDG-10137
TPS51916
www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012
APPLICATION INFORMATION
VDDQ Switch Mode Power Supply Control
The TPS51916 supports two SMPS control architectures, D-CAP™ mode and D-CAP2™ mode. Both control
modes do not require complex external compensation networks and are suitable for designs with small external
components counts. The D-CAP™ mode provides fast transient response with appropriate amount of equivalent
series resistance (ESR) on the output capacitors. The D-CAP2™ mode is dedicated for a configuration with very
low ESR output capacitors such as multi-layer ceramic capacitors (MLCC). For the both modes, an adaptive on-
time control scheme is used to achieve pseudo-constant frequency. The TPS51916 adjusts the on-time (t
ON
) to
be inversely proportional to the input voltage (V
IN
) and proportional to the output voltage (V
VDDQ
). This makes a
switching frequency fairy constant over the variation of input voltage at the steady state condition. These control
modes and switching frequencies are selected by the MODE pin described in Table 2.
VREF and REFIN, VDDQ Output Voltage
The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-μA (max)
current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of
0.1-μF or larger should be attached close to the VREF terminal.
The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range
between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See External
Components Selection section.) A few nano farads of capacitance from REFIN to GND is recommended for
stable operation.
Soft-Start and Powergood
Provide a voltage supply to VIN and V5IN before asserting S5 to high. TPS51916 provides integrated VDDQ
soft-start functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal
reference voltage ramping up. Figure 34 shows the start-up waveforms. The switching regulator waits for 400μs
after S5 assertion. The MODE pin voltage is read in this period. A typical VDDQ ramp up duration is 700μs.
TPS51916 has a powergood open-drain output that indicates the VDDQ voltage is within the target range. The
target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for
assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The
PGOOD start-up delay is 2.5 ms after S5 is asserted to high. Note that the time constant which is composed of
the REFIN capacitor and a resistor divider needs to be short enough to reach the target value before PGOOD
comparator enabled.
Figure 34. Typical Start-up Waveforms
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