Datasheet
1
2
3
4
TPS51604
SKIP
VDD
BST
DRVH
SW
GND
5 DRVL
8
7
6
PWM
TPS51604
SLUSBA6A –DECEMBER 2012–REVISED AUGUST 2013
www.ti.com
DSG
8 PINS
(TOP VIEW)
PIN FUNCTIONS
PIN
I/O
(1)
DESCRIPTION
NAME NO.
BST 1 I High-side N-channel FET bootstrap voltage input; power supply for high-side driver.
DRVH 8 O High-side N-channel gate drive output.
DRVL 5 O Synchronous low-side N-channel gate drive output
GND 6 – Synchronous low-side N-channel gate drive return and IC reference.
PWM 2 I PWM input. A tri-state voltage on this pin turns OFF both the high-side (DRVH) and low-side drivers (DRVL)
When SKIP is LO, the zero crossing comparator is active; the power chain enters discontinuous conduction
SKIP 3 I mode when the inductor current reaches zero. When SKIP is HI, the zero crossing comparator is disabled, and
the driver outputs follow the PWM input. A tri-state voltage on SKIP puts the driver into a very low power state.
SW 7 I/O High-side N-channel gate drive return. Also, zero-crossing sense input.
VDD 4 I 5-V power supply input; decouple to GND with a ceramic capacitor with a value of 1 µF or greater.
Thermal Pad – Tie to system GND plane with multiple vias.
(1) I=Input, O=Output
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