Datasheet

PWM
DRVH
UDG-12227
DRVL
1.0 V
1.0V
t
R-DT
t
F-DT
1.0 V
Time
PWM
DRVH
t
R-DRVL
Time
UDG-12226
DRVL
t
F-DRVL
t
RPD-DRVL
t
FPD-DRVH
90%
2.65 V
4.0 V
1.0 V
10%
4.0 V
1.0 V
0.6 V
90%
4.0 V
1.0 V
10%
4.0 V
1.0 V
t
R-DRVL
t
FPD-DRVL
t
F-DRVH
t
RPD-DRVH
TPS51604
SLUSBA6A –DECEMBER 2012–REVISED AUGUST 2013 www.ti.com
Adaptive Deadtime Control and Shoot-Through Protection
The driver utilizes an anti-shoot-through and adaptive dead-time control to minimize low-side body diode
conduction time and maintain high efficiency. When the PWM input voltage becomes high, the low-side MOSFET
gate voltage begins to fall after a propagation delay. At the same time, DRVL voltage is sensed, and high-side
driving voltage starts to increase after DRVL voltage is lower than a proper threshold.
Figure 17. Rise/Fall Timing and Propagation Delay Definitions
Normal operation manages to near zero the dead-time between the low-side gate turn-off to high-side gate
voltage turn-on and high-side gate turn-off to low-side gate turn-on in order to avoid simultaneous conduction of
both MOSFETs as well as to reduce body diode conduction and recovery losses. This also reduces ringing on
the leading edge of the SW waveform.
Figure 18. Dead-Time Definitions
Integrated Boost-Switch
To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the
conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL
signal.
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