Datasheet

t
FPD-DRVL
Time
UDG-12225
High-Z Window
High-Z High-Z
LDR
PWM
HDR
High-Z Window
V
IH
V
IL
t
R-DT
t
FPD-DRVH
t
F-DT
t
HOLD_OFF1
t
3RD1
t
HOLD_OFF2
t
3RD2
TPS51604
www.ti.com SLUSBA6A –DECEMBER 2012–REVISED AUGUST 2013
Figure 16. PWM Tri-State Timing Diagram
SKIP Pin
The SKIP pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP is
low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current
is less than the critical current. When SKIP is high, the ZX comparator disables, and the converter enters FCCM
mode. When both SKIP and PWM are tri-stated, normal operation forces the gate driver outputs low and the
driver enters a very-low-power state. In the low-power state, the UVLO comparator remains off to reduce
quiescent current. When either SKIP is pulled low, the driver wakes up and is able to accept PWM pulses in less
than 50µs.
Table 1 shows the logic functions of UVLO, PWM, SKIP DRVH and DRVL.
Table 1. Logic Functions of the TPS51604
UVLO PWM SKIP DRVL DRVL MODE
Active — — Low Low Disabled
Inactive Low Low High
(1)
Low DCM
(1)
Inactive Low High High Low FCCM
Inactive High H or L Low High
Inactive Tri-state H or L Low Low Low power
Inactive — Tri-state Low Low Very Low power
(1) Until zero crossing protection occurs.
Zero Crossing (ZX) Operation
The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy
load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,
which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects
the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the
rectifying MOSFET.
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