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Test Procedure

Table 5. VID Bits Selection (continued)

3-Bit VID Table (1 = 1VBIAS, 0 = GND)

VID2 VID1 VID0 Vout (V)

1 1 1 0.70

5.5 Sleep Mode Selection (SLP)

The SLP can be set by J5 (SLP).

Default setting Jumper on pin2 and pin3 of J5 to disable the SLP mode.

Table 6. SLP Mode Selection

Jumper set to SLP mode selection

2-3 pin shorted Disable SLP mode

1-2 pin shorted Enable SLP mode

5.6 1.2-V Output Voltage Option (J10: Vout selection)

The 1.2-V output can be set by J10 (Vout Select).

Default setting : Jumper shorts on J10 to set 0.7 V to 1.05-V output.

Table 7. 1.2-V Output Option Selection

Jumper Set to Output Range

No Jumper 1.2-V Output

Jumper shorted 0.70 V to 1.05 V controlled by 3-bit VID

6 Test Procedure

6.1 Line/Load Regulation and Efficiency Measurement Procedure

1. Ensure that Load is set to constant resistance mode and to sink 0 Adc.

2. Ensure that the jumper provided with the EVM on J6 is present before Vin is applied.

3. Increase Vin from 0 V to 12 V. Using V1 to measure input voltage.

4. Remove the jumper on J6 to enable the controller.

5. Vary Load from 0 Adc to 20 Adc, Vout must remain in load regulation.

6. Vary Vin from 8 V to 14 V; Vout must remain in line regulation.

7. Put the jumper on J6 to disable the controller.

8. Decrease Load to 0 A

9. Decrease Vin to 0 V.

6.2 List of Test Points

Table 8. Functions of Each Test Points

Test Points Name Description

TP1 Vin 12 Vin

TP2 GND 12 Vin Ground

TP3 SW Switching Node

TP4 GND Ground

TP5 Vout Vout

TP6 IMON Current Monitor Output, Refer to section 8.4

TP7 GND Ground

SLVU358–February 2010 Using the TPS51513EVM-549 A Single-Phase, D-CAP+™ Synchronous Buck

Controller With Integrated Drivers for General IC V

CORE

Applications

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