Datasheet

OUT
RIPPLE
V
V 15 mV
0.75
æ ö
= ´
ç ÷
è ø
f
SW
0
OUT
1
f
2 ESR C 4
= £
p ´ ´
R1
R2
VoltageDivider
+
V
FB
+
0.75V
PWM
Control
Logic
and
Divider
V
IN
Lx
ESR
C
O
V
C
R
L
I
L
I
O
UDG-09062
I
C
SwitchingModulator
Output
Capacitor
Not Recommended for New Designs
TPS51315
SLUS881B –MAY 2009–REVISED AUGUST 2012 www.ti.com
APPLICATION INFORMATION
Loop Compensation and External Parts Selection
Figure 25. Simplified Modulator Block Diagram
The feedback voltage (V
VFB
) is compared to the internal reference voltage after the divider resistors. The PWM
comparator determines when to turn on the upper MOSFET. The gain and speed of the comparator is high
enough to maintain the voltage level relatively constant at the beginning of each on cycle, or at the end of each
off cycle . The dc output voltage may have line regulation due to ripple amplitude that slightly increases as the
input voltage increases.
For loop stability, the 0 dB frequency, f
0
, defined in Equation 6 must be lower than 1/4 of the switching frequency.
(6)
Because f
0
is determined solely by the output capacitor characteristics, the loop stability of the D-CAP™ Mode is
determined by capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have and output
capacitance on the order of several hundred micro-farads and and ESR of approximately 10 mΩ. These values
make f
0
on the order of 100 kHz or less and create a stable loop. However, ceramic capacitors have an f
0
of
more than 700 kHz, which is not suitable for this operating mode, although the D-CAP™ Mode provides many
advantages such as ease-of-use, minimum external component configuration, and extremely short response
time. These advantages are realized because there is no error amplifier in the loop, so a sufficient feedback
signal is required from an external circuit to reduce the jitter level. The required signal level is approximately 15
mV at the comparing point. This generates output ripple at the output node that can be calculated in Equation 7.
The output capacitor ESR should meet this requirement.
(7)
For applications with all ceramic output capacitors, a few external components need to be added to ensure the
loop stability. Please refer to Figure 29. Since ceramics capacitors have low ESR, feedback ripple in phase with
inductor current is recommended. R-C network across the output inductor can mimic inductor current when RC ≈
L / DCR, the ripple current can be coupled to the feedback through a 1-μF capacitor.
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