Datasheet
SLVS426 − MAY 2002
www.ti.com
9
DETAILED DESCRIPTION
PWM OPERATION
The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck converter. The
output voltage of the SBRC is fed back to the inverting input (INVx (x=1,2,3)) of the error amplifier. The noninverting input
is internally connected to a 0.85-V precise band gap reference circuit. The unity gain bandwidth of the amplifier is 2.5 MHz.
This decreases the amplifier delay during fast load transients and contributes to a fast response. Loop gain and phase
compensation is programmable by an external C, R network between the FBx and INVx pins. The output signal of the error
amplifier is compared with a triangular wave to achieve the PWM control signal. The oscillation frequency of this triangular
wave sets the switching frequency of the SBRC and is determined by the capacitor connected between the CT and GND
pins. The PWM mode is used for the entire load range if the PWM_SEL pin is set LOW, or used in high output current
condition if auto PWM/SKIP mode is selected by setting the same pin to HIGH.
SKIP MODE OPERATION
The PWM_SEL pin selects either the auto PWM/SKIP mode or fixed PWM mode. If this pin is lower than 0.3-V, the SBRC
operates in the fixed PWM mode. If 2.5 V (min.) or higher is applied, it operates in auto PWM/SKIP mode. In the auto
PWM/SKIP mode, the operation changes from constant frequency PWM mode to an energy-saving SKIP mode
automatically in accordance with load conditions. Using a MOSFET with ultra-low r
DS(on)
when the auto SKIP function is
implemented is not recommended. The SBRC block has a hysteretic comparator to regulate the output voltage of the
synchronous buck converter during SKIP mode. The delay from the comparator input to the driver output is typically 1.2
µs. In the SKIP mode, the frequency varies with load current and input voltage.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current and low r
DS(on)
N-channel MOSFET(s). The current rating of the driver
is 1.2 A at source and sink. When configured as a floating driver, a 5-V bias voltage is delivered from VREF5 pin. The
instantaneous drive current is supplied by the flying capacitor between the LHx and LLx pins since a 5-V power supply does
not usually have low impedance. It is recommended to add a 5 Ω to 10 Ω resistor between the gate of the high-side
MOSFET(s) and the OUTx_u pin to suppress noise. The maximum voltage that can be applied between the LHx and
OUTGNDx pins is 33 V.
When selecting the high current rating MOSFET(s), it is important to pay attention to both gate drive power dissipation and
the rise/fall time against the dead-time between high-side and low-side drivers. The gate drive power is dissipated from
the controller IC and it is proportional to the gate charge at V
GS
= 5 V, PWM switching frequency, and the numbers of all
MOSFETs used for low-side and high-side switches. This gate drive loss should not exceed the maximum power dissipation
of the device.
LOW-SIDE DRIVER
The low-side driver is designed to drive high current and low r
DS(on)
N-channel MOSFET(s). The maximum drive voltage
is 5 V from the internal regulator or REG5V_IN pin. The current rating of the driver is typically 1.5 A at source and sink.
Gate resistance is not necessary for the low-side MOSFET for switching noise suppression since it turns on after the
parallel diode is turned on (ZVS). It needs the same dissipation consideration when using high current rating MOSFET(s).
Another issue that needs precaution is the gate threshold voltage. Even though the OUTx_d pin is shorted to the OUTGNDx
pin with low resistance when the low-side MOSFET(s) is OFF, high dv/dt of the LLx pin during turnon of the high-side arm
will generate a voltage peak at the OUTx_d pin through the drain to gate capacitance, C
dg
, of the low-side MOSFET(s).
To prevent a short period shoot-through during this switching event, the application designer should select MOSFET(s) with
adequate threshold voltage.