Datasheet


SLVS426 − MAY 2002
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23
Connections
D Connections from the drivers to the gate of the power MOSFETs should be as short and wide as possible
to reduce stray inductance. This becomes more critical if external gate resistors are not being used. In
addition, as for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s) considerably
reduces the noise at the LL node, improving the performance of the current limit function.
D The connection from LL to the power MOSFETs should be as short and wide as possible.
Bypass Capacitor
D The bypass capacitor for VIN_SENSE should be placed close to the TPS5130.
D The bulk storage capacitors across VIN should be placed close to the power MOSFETs. High-frequency
bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain
of the high-side MOSFET(s) and to the source of the low-side MOSFET(s).
D For aligning phase between the drain of high-side MOSFET(s) and the trip-pin, and for noise reduction, a
0.1 µF capacitor C
(TRIP)
should be placed in parallel with the trip resistor.
Bootstrap Capacitor
D The bootstrap capacitor C
(BS)
(connected from LH to LL) should be placed close to the TPS5130.
D LH and LL should be routed close to each other to minimize noise coupling to these traces.
D LH and LL should not be routed near the control pin area (ex. INV, FB, REF, etc.).
Output Voltage
D The output voltage sensing trace should be isolated by either ground plane.
D The output voltage sensing trace should not be placed under the inductors on same layer.
D The feedback components should be isolated from output components, such as, MOSFETs, inductors, and
output capacitors. Otherwise the feedback signal line is susceptible to output noise.
D The resistors for setup output voltage should be referenced to ANAGND.
D The INV trace should be as short as possible.
Figure 19
0
20
40
60
80
100
0.01 0.1 1 10
V
IN
= 8 V
V
IN
= 12 V
V
IN
= 20 V
I
O
− Output Current − A
Efficiency (PWM MODE) − %
EFFICIENCY (PWM MODE)
vs
OUTPUT CURRENT
SBRC CH1
External 5 V
V
O
1 = 3.3 V
Figure 20
0
20
40
60
80
100
0.01 0.1 1 10
V
IN
= 8 V
V
IN
= 12 V
V
IN
= 20 V
I
O
− Output Current − A
Efficiency (PWM MODE) − %
EFFICIENCY (PWM MODE)
vs
OUTPUT CURRENT
SBRC CH2
External 5 V
V
O
2 = 5 V
Figure 21
0
20
40
60
80
100
0.01 0.1 1 10
V
IN
= 8 V
V
IN
= 12 V
V
IN
= 20 V
I
O
− Output Current − A
Efficiency (PWM MODE) − %
EFFICIENCY (PWM MODE)
vs
OUTPUT CURRENT
SBRC CH3
External 5 V
V
O
3 = 1.8 V