Datasheet

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SLVS426 − MAY 2002
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22
Layout Guidelines
Good power supply results only occur when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens amps, good power supply layout is much more difficult than most general
PCB designs. The general design should proceed from the switching node to the output, then back to the driver
section and, finally, parallel the low-level components. Below are specific points to consider before the layout
of a TPS5130 design begins.
D A four-layer PCB design is recommended for design using the TPS5130. For the EVM design, the top layer
contains the interconnection to the TPS5130, plus some additional signal traces. Layer2 is fully devoted
to the ground plane. Layer3 has some signal traces. The bottom layer is almost devoted to ANAGND, and
the rest is to other signal trace.
D All sensitive analog components such as INV, REF, CT, GND, FLT, and SS_STBY should be referenced
to ANAGND.
D Ideally, all of the area directly under the TPS5130 chip should also be ANAGND.
D ANAGND and DRVGND should be isolated as much as possible, with a single point connection between
them.
LDO_OUT
LDO_GATE
LDO_CUR
LDO_IN
VIN_SENSE
OUTGND
OUT_d
LL
OUT_u
INV_LDO
FLT
REF
GND
CT
SOFT_START
FB
INV Vox
VIN
Vo_LDO
VoxGND
ANAGND
DRVGND
LH
VREF5
TRIP
C
TRIP
C
BS
C
BP
C
IN
C
OUT
Figure 18. PCB Diagram
Low-Side MOSFET(s)
D The source of low-side MOSFET(s) should be referenced to DRVGND, otherwise ANAGND is subject to
the noise of the outputs.
D DRVGND should be connected to the main ground plane close to the source of the low-side MOSFET.
D OUTGND should be placed close to the source of low side MOSFET(s).
D The Schottky diode anode, the returns for the high frequency bypass capacitor for the MOSFETs, and the
source of the low-side MOSFET(s) traces should be routed as close together as possible.