Datasheet


SLVS426 − MAY 2002
www.ti.com
21
Undervoltage Protection
The undervoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the
voltage at either pin falls below 65 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. if
the fault condition persists beyond the time t
(uvplatch)
, the fault latch is set and both the high-side and low-side
drivers, and LDO regulator drivers are forced OFF.
Short-Circuit Protection
The short-circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current limit
circuit limits the output current, then the output voltage goes below the target output voltage and UVP
comparator detects a fault condition as described above.
Overvoltage Protection
The overvoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage
at either pin rises above 112 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. If the fault
condition persists beyond the time t
(ovplatch)
, the fault latch is set and the high-side drivers are forced OFF, while
the low-side drivers are forced ON, and LDO regulator drivers are forced OFF.
CAUTION:
Do not set the FLT terminal to a lower voltage (or GND) while the device is timing out an OVP or UVP
event. If the FLT terminal is manually set to a lower voltage during this time, output overshoot may
occur. The TPS5130 must be reset by grounding SS_STBYx and STBY_LDO, or dropping down
REG5V_IN.
Disablement of the Protection Function
If it is necessary to inhibit the protection functions of the TPS5130 for troubleshooting or other purposes, the
OCP,OVP, and UVP circuits may be disabled.
D OCP(SBRC): Remove the current limit resistors R17, R23 and R24 to disable the current limit function.
D OCP(LDO): Short−circuit R21 to disable the current limit function.
D OVP, UVP: Grounding the FLT terminal can disable OVP and UVP.
LDO REGULATOR APPLICATION INFORMATION
Output Capacitor Selection
To keep stable operation of the LDO, capacitance of more than 33 µF and R
(esr)
of more than 30 mΩ are
recommended for the output capacitor.
Power MOSFET Selection
Also, to keep stable operation of LDO, lower input capacitance is recommended for the external power
MOSFET. However, input capacitance that is too small may lead the feedback loop into an unstable region.
In this case, the gate resistor of several hundreds ohms keeps the LDO operation in the stable state.
Current Protection
If excess output current flows through sense resistor (R21) and the voltage drop exceeds 50 mV, the output
voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer.
When the set current is 3 A, the value of R21 is 16.7 mΩ.