Datasheet


SLVS426 − MAY 2002
www.ti.com
17
APPLICATION INFORMATION
The design shown is a reference design for a notebook PC application. An evaluation module (EVM) is available
for customer testing and evaluation.
The following key design procedures aid in the design of the notebook PC power supply using TPS5130.
1
2
3
4
5
6
7
8
9
10
11
12
U01
TPS5130PT
VO3−2
VO3−1
LDO_OUT−2
LDO_OUT−1
GND−2
GND−1
VIN1−2
VIN1−1
VREF5
VREF3.3
VO2−2
VO2−1
VO1−2
VO1−1
C45
C27
Q07A Q07B
R21A
R21B
R21C
R07
C09
C08
C07
C05
C04
R06
R01A
R01B
R02
C02
R05
JP03
JP04
1
2
3
1
2
3
1
2
3
PWR_GD
13 14 15
16 17 18
19 20 21 22 23 24
STBY_LDO
STBY_VREF3.3
STBY_VREF5
REF
GND
CT
PWM_SEL
SS_STBY2
FB2
INV2
SS_STBY1
FB1
OUTGND3 OUT3_d LL3 OUT3_u LH3 VIN_SENSE3 TRIP3 PG_DELAY PGOUT INV3 FB3 SS_STBY3
27
26
25
30
29
28
33
32
31
36
35
34
INV_LDO
LDO_OUT
LDO_GATE
LDO_CUR
LDO_VIN
REG5V_IN
VREF5
VREF3.3
VIN
LH2
OUT2_u
LL2
39 38 37 42 41 40 45 44 43 48 47 46
OUT2_d
OUTGND2
TRIP2
VIN_SENSE12
TRIP1
OUTGND1
OUT1_d
LL1
OUT1_u
LH1
FLT
INV1
4
5 − 8
1 − 3
1
2
3
L02
D03
Q03A Q03B
Q04A Q04B
4
5 − 8
1 − 3
4
5 − 8
1 − 3
4
5 − 8
1 − 3
4
5 − 8
1 − 3
L01
D02
Q01A Q01B
Q02A Q02B
4
5 − 8
1 − 3
4
5 − 8
1 − 3
4
5 − 8
1 − 3
4
5 − 8
1 − 3
C39C38C37
C32C31
L03
D05
Q05A Q05B
Q06A Q06B
4
5 − 8
1 − 3
4
5 − 8
1 − 3
4
5 − 8
1 − 3
4
5 − 8
1 − 3
C18C17
C01B
C24
C06
R08
JP05
JP06
1
2
3
1
2
3
R03A
R03B
R04
C03
1
2
3
1
2
3
1
2
3
LDO_IN
C22
C26
R18
R19
R32
R33R34
Q10
D09C19 C20
C23
C01A
R20
D08C33 C34
D07 C40
2SC4617
R29
R30R31
Q09
2SC4617
R26
R27R28
Q08
2SC4617
D04
R22
D01
R25
C41
C35
C29
C15
R23
R24
C43
C44
C42
R09
R49
R46
R47
C16
C30
Q11
Q12
JP01
JP02
JP11
JP12
R48
C36
Q13
JP07
JP13
C10
R11
R12
C11
R14
R13
R14B
C12
R15
R17
C21
C14
C13
D06
R16
JP10
VIN_SLIT
JP08
C28
Figure 17. EVM Schematic
An optional circuit composed of Q08, Q09, Q10, R26, R27, R28, R29, R30, R31, R32, R33, and R34 can be
used to increase temperature coefficient of the trip current.
OUTPUT VOLTAGE SETPOINT CALCULATION
In the following calculation, assume the output voltage of SBRC1 (V
O
1), SBRC2 (V
O
2), SBRC3 (V
O
3), and LDO
(V
O
4) are 3.3 V, 5 V, 1.8 V, and 1.5 V respectively. The reference voltage and the voltage divider set the output
voltage. In the TPS5130, the reference voltage is 0.85 V, and the divider is composed of three resistors in the
EVM design that are R01A, R01B, and R05 for the first SBRC output; R03A, R03B, and R07 for the second
SBRC output ; R14A, R14B, and R11 for the third SBRC output ; R18 and R19 for LDO regulator output.
V
O
+
R1 V
ref
R2
) V
ref
or R2 +
R1 V
ref
V
O
* V
ref
where R1 is the top resistor (kΩ) (R01A + R01B or R03A + R03B or R14A + R14B or R18); R2 is the bottom
resistor (kΩ) (R05 or R07 or R11 or R19); V
O
is the required output voltage (V); V
ref
is the reference voltage
(0.85 V in TPS5130). The value for R1 is set as a part of the compensation circuit and the value of R2 may be