Datasheet
SLVS426 − MAY 2002
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12
UNDER VOLTAGE LOCK OUT (UVLO)
When the output voltage of the internal 5-V regulator or the REG5V_IN voltage decreases below about 4 V, the output
stages of all the SBRCs and the LDO are turned off. This state is not latched, and the operation recovers immediately after
the input voltage becomes higher than the turnon value again. The typical hysteresis voltage is 100 mV.
UVLO FOR LDO
The LDO_IN voltage is monitored with a hysteretic comparator. When this voltage is less than 1 V, the UVLO circuit disables
the UVP/OVP comparators that monitor the INV_LDO voltage. In case the SBRC overcurrent protection is activated prior
to that of the LDO’s, this protection function may also be observed.
LDO CONTROL
The LDO controller can drive an external N-channel MOSFET. This realizes a fast response as well as an ultralow dropout
voltage regulator. For example, it is easy to configure both a 1.8-V and a 1.5-V high current power supply for core and I/O
of modern digital processors, one from the SBRC and the other from the LDO. The LDO_IN voltage range is from 1.1 V
to 3.6 V, and the output voltage is adjustable from 0.9 V to 2.5 V by an external resistor divider. Gain and phase of the
high-speed error amplifier for this LDO control is internally compensated and is connected to the 0.85-V band gap reference
circuit. The gate driver buffer is supplied by VIN_SENSE voltage. In the relatively high output voltage applications, make
sure that output voltage plus threshold voltage of the pass transistor is less than the minimum VIN. More precisely,
VIN - 0.7 ≥ V
thn
+ V
(LDO_OUT)
where V
thn
is the threshold voltage of the Nch MOSFET.
The LDO controller is also equipped with OVP, UVP, overcurrent limit, and overshoot protection functions.
OVERSHOOT PROTECTION
In the event that load current changes from high to low very quickly, the LDO regulator output voltage may start to overshoot.
In order to resist this phenomenon, the LDO controller has an overshoot protection function. If the LDO regulator output
overshoots, the controller draws electrical charge out from the LDO_OUT pin to hold it stable.
POWERGOOD
A single powergood circuit monitors the SBRCx output voltages and the LDO output voltage. The powergood pin is an open
drain output. When the INV or INV_LDO voltage goes beyond ±7% of 0.85 V, the powergood pin is pulled down to the LOW
level. Powergood propagation delay is programmable by controlling rising time using an external capacitor connected to
the PG_DELAY pin. During the soft start period, powergood indicates LOW, in other words power bad.
Table 3. Powergood Logic
SS_STBY1 SS_STBY2 SS_STBY3 STBY_LDO POWERGOOD
L L L L L
H L L L H
L H L L H
H H L L H
L L H L H
H L H L H
L H H L H
H H H L H
H or L H or L H or L H H