Datasheet

SLUU182 − March 2004
18
High-Performance Dual Synchronous Buck Conversion Using the TPS5124
• LH and LL should not be routed near the control pin area (e.g. INV, FB, REF, etc.).
6.5 Output voltage
•
The output voltage sensing trace should be isolated by either ground plane.
• The output voltage sensing trace should not be placed under the inductors on the same
layer.
• The feedback components should be isolated from output components, such as, MOSFETs,
inductors, and output capacitors. Otherwise the feedback signal line is susceptible to output
noise.
• The resistors to set up the output voltage should be referenced to ANAGND.
• The INV trace should be as short as possible.
7 PCB layout
Figures 14 through 18 shows the PCB layout.
Figure 14. Top Assembly