Datasheet

SLUU182 − March 2004

High-Performance Dual Synchronous Buck Conversion Using the TPS5124

6 Layout Guidelines

Proper design and layout is crucial to the performance of the power supply. Here are some

suggestions to the layout of TPS5124 design.

• A four−layer PCB design is recommended for designs using the TPS5124. Use at least one

layer dedicated to the PWRGND plane.

• All sensitive analog components such as INV, REF, CT, GND, SCP and SOFTSTART should

be reference to ANAGND.

• Ideally, all of the area directly under TPS5124 chip should also be ANAGND.

• ANAGND and PWRGND should be isolated as much as possible, with a single point

connection between them

6.1 Low side MOSFET(s)

•

The source of low-side MOSFET(s) should be referenced to PWRGND. Otherwise ANAGND

is subject to the noise of the outputs.

• PWRGND should be placed close to the source of low-side MOSFET(s).

6.2 Connections

•

Connections from the drivers to the gate of the power MOSFETs should be as short and

wide as possible to reduce stray inductance. This becomes more critical if external gate

resistors are not used. In addition, external gate resistor for the high-side FET(s) will

considerably reduce the noise at the LL node and improve the performance of the current

limit function.

• The connection from LL to the power MOSFET(s) should be as short and wide as possible.

6.3 Bypass capacitor

•

The bypass capacitor for VCC should be placed close to the TPS5124.

• The bulk storage capacitors across VCC should be placed close to the power MOSFETs.

High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and

connected close to the drain of the high-side MOSFET(s) and to the source of the low-side

MOSFET(s).

• For noise reduction, a 0.1-µF capacitor C

TRIP

should be placed in parallel with the trip

resistor R

6.4 Bootstrap capacitor

•

The bootstrap capacitor CBS (connected from LH to LL) should be placed close to the

TPS5124.

• LH and LL should be routed close to each other to minimize noise coupling to these traces.