Datasheet

TPS51220A
www.ti.com SLUS897E –DECEMBER 2008–REVISED JANUARY 2013
PIN FUNCTIONS (continued)
PIN
I/O DESCRIPTION
NAME NO.
Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for
RF 3 I/O
synchronization.
Control architecture and OVP functions selection pin.
GND: Current mode, OVP enable
FUNC 11 I
VREF2: D-CAP mode, OVP disable
VREG3: D-CAP mode, OVP enable
VREG5: Current mode, OVP disable
VREF2 13 O 2-V reference output. Bypass to (signal) GND with 0.22-μF of ceramic capacitance.
Overcurrent trip level and discharge mode selection pin.
GND: V
(OCL-ULV)
, discharge on
TRIP 14 I
VREF2: V
(OCL-ULV)
, discharge off
VREG3: V
(OCL-LV)
, discharge off
VREG5: V
(OCL-LV)
, discharge on
VREF2 and VREG5 linear regulators enable pin. When turning on, apply greater than 1.2 V and less than 6
EN 12 I
V. Connect to GND to disable.
VBST1 31 Supply inputs for high-side N-channel FET driver (boot strap terminal). Connect a capacitor (0.1-μF or
I greater is recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this
VBST2 26
pin is an optional.
DRVL1 30
O Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, and GND referenced driver.
DRVL2 27
VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW
voltage is higher than 4.8 V, switch-over function is enabled.
V5SW 2 I
Note: When switch-over is enabled, VREG5 output voltage is approximately equal to the V5SW input
voltage.
5-V, 100-mA low dropout linear regulator output. Bypass to (power) GND using a 10-μF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
VREG5 29 O when 4.8 V or above is provided.
Note: When switch-over (see above V5SW) is enabled, VREG5 output voltage is approximately equal to
V5SW input voltage.
VIN 23 I Supply input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
GND 28 – Ground
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