Datasheet

InnerSignal-GNDplane
0W resistor
GND
Toinner
Power-GND
layer
Toinner
Signal-GND
plane
#28
GND-pin
RCnetwork
nexttoIC
Currentsensing
Device
TPS51220A
SLUS897E –DECEMBER 2008–REVISED JANUARY 2013 www.ti.com
sensing comparator inputs (CSPx and CSNx). (See Figure 52)
Figure 52. Current Sensing Traces
• Use small copper space for VFBx. These are short and narrow traces to avoid noise coupling
• Connect VFB resistor trace to the positive node of the output capacitor.
• Use signal GND for VREF2 and VREG3 capacitors, RF and VFB resistors, and the other sensitive analog
components. Placing a signal GND plane (underneath the IC, and fully covered peripheral components) on
the internal layer for shielding purpose is recommended. (See Figure 53)
• Use a thermal land for PowerPAD™. Five or more vias, with 0.33-mm (13-mils) diameter connected from the
thermal land to the internal GND plane, should be used to help dissipation. Do NOT connect the GND-pin to
this thermal land on the surface layer, underneath the package.
Routing (power portion)
• Use wider/shorter traces of DRVL for low-side gate drivers to reduce stray inductance.
• Use the parallel traces of SW and DRVH for high-side MOSFET gate drive, and keep them away from DRVL.
• Connect SW trace to source terminal of the high-side MOSFET.
• Use power GND for VREG5, VIN and V
OUT
capacitors and low-side MOSFETs. Power GND and signal GND
should be connected near the device GND terminal. (See Figure 53)
Figure 53. GND Layout Example
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