Datasheet
Co u
3
2p ESR ƒsw
ƒ
0
+
1
2p ESR Co
t
ƒsw
3
Co u
15
p
I
OCL(PEAK)
1
V
OUT
Gmv Rgv
ƒsw
ƒ
0
+
5
p
I
OCL(PEAK)
1
V
OUT
Gmv Rgv
Co
t
ƒsw
3
Rgv[kW] + 200
I
OUT(MAX)
I
OCL(PEAK)
V
OUT
[V]
Vdroop[mV]
Rgv + 0.1
I
OUT(MAX)
I
OCL(PEAK)
V
OUT
1
Gmv Vdroop
R
SENSE
+
V
OCL
I
OCL(PEAK)
IN(TYP) OUT OUT
OUT(MAX) SW IN(TYP)
(V - V ) × V
1
L = ×
0.33 x I x Vf
TPS51220A
SLUS897E –DECEMBER 2008–REVISED JANUARY 2013
www.ti.com
3. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to
40% at the typical input voltage condition, next equation uses 33%.
(9)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation.
4. Determine the OCL trip voltage threshold, V
(OCL)
, and select the sensing resistor.
The OCL trip voltage threshold is determined by TRIP pin setting. To use a larger value improves the S/N
ratio. Determine the sensing resistor using next equation. I
OCL(PEAK)
should be approximately 1.5 × I
OUT(MAX)
to 1.7 × I
OUT(MAX)
.
(10)
5. Determine Rgv. Rgv should be determined from preferable droop compensation value and is given by next
equation based on the typical number of Gmv = 500μS.
(11)
(12)
If no-droop is preferred, attach a series RC network circuit instead of single resistor. Series resistance is
determined using Equation 12 . Series capacitance can be arbitrarily chosen to meet the RC time constant,
but should be kept under 1/10 of f
o
. For D-CAP mode, Rgv is used for adjusting ramp compensation. 10kΩ is
a good value to start design with. 6kΩ to 20kΩ can be chosen.
6. Determine output capacitance Co to achieve a stable operation using the next equation. The 0 dB frequency,
f
o
, should be kept under 1/3 of the switching frequency.
(13)
(14)
For D-CAP mode, f
o
is determined by the output capacitor’s characteristics as below.
(15)
(16)
For better jitter performance, a sufficient amount of feedback signal is required at VFBx pin. The
recommended signal level is approximately 30mV per t
sw
(switching period) of the ramping up rate, and more
than 4 mV of peak-to-peak voltage.
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