Datasheet

I
LL(DC)
Time
Inductor
Current
I
LL(PEAK)
I
IND(RIPPLE)
0
( )
( )
LL(PEAK)RAMP SW
OCL PEAK
I 0.2 - 0.13 t f I= ´ ´ ´
IN OUT OUT
IND(RIPPLE)
SW IN
(V - V ) × V
1
I = ×
L × Vf
I
LL(DC)
+ I
LL(PEAK)
* 0.5 I
IND(RIPPLE)
TPS51220A
SLUS897E –DECEMBER 2008–REVISED JANUARY 2013 www.ti.com
In both cases, the TPS51220A shows jitter inherent to the blanking time. Since the device is a fixed frequency
controller, the rising edge of the switching node is settled at the clock cycle. Consequently, jitter is observed at a
period of switching node falling edge. This jitter does not represent small signal instability. In fact, jittering is a
normal action of control loop against timing deviation caused by any accidental event such as noise, or the
blanking time, adjusting back to the regulation point. A small amount of jittering does not harm the voltage
regulation. However; if the user wants a further reduction of jitter, using the external clock synchronization
provides adjustable phase shift between channels to avoid overlapping of switching events. See the PWM
Frequency Control section.
LIGHT LOAD OPERATION
The TPS51220A automatically reduces switching frequency at light load conditions to maintain high efficiency if
Auto Skip or Out-of-Audio™ mode is selected by SKIPSELx. This reduction of frequency is achieved by skipping
pulses. As the output current decreases from heavy load condition, the inductor current is also reduced and
eventually comes to the point that its peak reaches a predetermined current, I
LL(PEAK)
, which indicates the
boundary between heavy-load and light-load conditions. Once the top MOSFET is turned on, the TPS51220A
does not allow it to be turned off until it reaches I
LL(PEAK)
. This eventually causes an overvoltage condition to the
output and pulse skipping. From the next pulse after zero-crossing is detected, I
LL(PEAK)
is limited by the ramp-
down signal I
LL(PEAK)RAMP
, which starts from 25% of the overcurrent limit setting (I
OCL(PEAK)
: (see the Current
Protection section) toward 5% of I
OCL(PEAK)
over one switching cycle to prevent causing large ripple. The
transition load point to the light load operation I
LL(DC)
can be calculated in Equation 2.
(2)
where
• f
SW
is the PWM switching frequency which is determined by RF resistor setting or external clock (3)
(4)
Switching frequency versus output current in the light load condition is a function of L, f, V
IN
and V
OUT
, but it
decreases almost proportionally to the output current from the I
LL(DC)
, as described in Equation 2; while
maintaining the switching synchronization with the clock. Due to the synchronization, the switching waveform in
boundary load condition (close to I
LL(DC)
) appears as a sub-harmonic oscillation; however, it is the intended
operation.
If SKIPSELx is tied to GND, the TPS51220A works on a constant frequency of f
SW
regardless its load current.
Figure 42. Boundary Between Pulse Skipping and CCM
24 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links :TPS51220A