Datasheet

TPS51219
www.ti.com SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
RECOMMENDED OPERATING CONDITIONS
MIN TYP MAX UNIT
Supply voltage V5 4.5 5.5 V
BST –0.1 33.5
BST
(1)
–0.1 5.5
SW -3 28
SW
(2)
–4.5 28
Input voltage range V
EN, TRIP, MODE –0.1 5.5
REFIN, VSNS, COMP –0.1 3.5
GSNS –0.3 0.3
PGND –0.1 0.1
DH –3 33.5
DH
(1)
–0.1 5.5
DH
(2)
–4.5 33.5
Output voltage range V
DL –0.1 5.5
PGOOD –0.1 5.5
VREF –0.1 3.5
T
A
Operating free-air temperature –40 85 °C
(1) Voltage values are with respect to the SW terminal.
(2) This voltage should be applied for less than 30% of the repetitive period.
THERMAL INFORMATION
TPS51219
THERMAL METRIC
(1)
RTE UNITS
16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
48.5
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
49.5
θ
JB
Junction-to-board thermal resistance
(4)
22.1
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.7
ψ
JB
Junction-to-board characterization parameter
(6)
22.1
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
7.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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