Datasheet
V
VSNS
V
REFIN
(1)
(2)
t
ON
t
OFF
Slope (2)
Jitter
20 mV
Slope (1)
Jitter
UDG-11010
V
REFIN
+Noise
Time
´
³
´
OUT
SW X
V ESR
20mV
f L
TPS51219
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SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that
determine jitter performance in D-CAP™ mode is the down-slope angle of the VSNS ripple voltage. Figure 26
shows, in the same noise condition, that jitter is improved by making the slope angle larger.
Figure 26. Ripple Voltage Slope and Jitter Performance
For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as
shown in Figure 26 and Equation 3.
where
• V
OUT
is the SMPS output voltage
• L
X
is the inductance (3)
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