Datasheet

4
+
2
g
M
=130 mS
VSNS
REFIN
1
VREF
Control
Logic
and
Driver
R1
R2
11
10
DH
DL
+
2.0 V
V
IN
Lx
ESR
C
OUT
R
LOAD
UDG-11009
V
OUT
5
COMP
C1
+
PWM
= £
p´ ´
SW
0
OUT
f
1
f
2 ESR C 3
£
p´
f
0
M
g
2 C1 10
TPS51219
SLUSAG1B – MARCH 2011– REVISED OCTOBER 2011 www.ti.com
D-CAP™ Mode
Figure 25 shows a simplified model of D-CAP™ mode architecture in the TPS51219.
Figure 25. Simplified D-CAP™ Model
The transconductance amplifier and the capacitance C1 configure an integrator. The VSNS voltage is compared
with REFIN voltage. Ripple voltage generated by ESR of the output capacitance is fed back through the C1 so
that C1 should be properly connected to the positive terminal of output capacitor, not at the remote point of load.
The PWM comparator creates a set signal to turn on the high-side MOSFET each cycle. The D-CAP™ mode
offers flexibility on output inductance and capacitance selections with ease-of-use without complex feedback loop
calculation and external components. However, it does require sufficient amount of ESR that represents inductor
current information for stable operation and good jitter performance. Organic semiconductor capacitor(s) or
specialty polymer capacitor(s) are recommended.
The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, f
0
, is
recommended to be lower than 1/3 of the switching frequency to secure proper phase margin. The integrator
time constant should be long enough compared to f
0
, for example one decade low, as described in Equation 2.
where
• ESR is the effective series resistance of the output capacitor
• C
OUT
is the capacitance of the output capacitor
• f
SW
is the switching frequency (1)
where
• g
M
is transconductance of the error amplifier (typically 130 µS) (2)
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