Datasheet

700 ms400 ms 1.4 ms
EN
VREF
V
OUT
PGOOD
UDG-11008
TPS51219
www.ti.com SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
Soft-Start and Powergood
Provide a voltage supply to VIN and V5 before asserting EN to high. TPS51219 provides integrated soft-start
functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal reference
voltage ramping up. Figure 24 shows the start-up waveforms. The switching regulator waits for 400μs after EN
assertion. The MODE pin voltage is read in this period. A typical V
OUT
ramp up duration is 700 μs.
THe TPS51219 has a powergood open-drain output that indicates the V
OUT
voltage is within the target range.
The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay
for assertion (low to high), and ±16% (typ) and 2-µs delay for de-assertion (high to low) during running. The
PGOOD start-up delay is 2.5 ms after EN is asserted to high. The time constant, which is composed of the
REFIN capacitor and a resistor divider, needs to be short enough to reach the target value before PGOOD
comparator enabled.
Figure 24. Typical Start-up Waveforms
MODE Pin Configuration
The TPS51219 reads the MODE pin voltage when the EN signal is raised high and stores the status in a
register. A 16.7-μA current is sourced from the MODE pin during this time to read the voltage across the resistor
connected between the pin and GND. Table 2 shows resistor values, corresponding control mode, switching
frequency and current sense operation configurations.
Table 2. MODE Selection
RESISTANCE BETWEEN CONTROL SWITCHING CURRENT SENSE
MODE NO.
MODE AND GND (kΩ) MODE FREQUENCY (kHz) OPERATION
7 200 400
R
DS(on)
6 100 300
D-CAP™
5 68 300
Resistor
4 47 400
3 33 500
Resistor
2 22 670
D-CAP2™
1 12 670
R
DS(on)
0 1 500
Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 15