Datasheet

R1
R2
Voltage Divider
+
V
FB
+
0.7 V
PWM
Control
Logic
and
Driver
V
IN
L
ESR
C
O
V
C
R
L
I
IND
I
OUT
UDG-09063
I
C
Switching Modulator
Output
Capacitor
DRVH
DRVL
V
OUT
O
1
H(s)
s ESR C
=
´ ´
f
SW
0
O
1
f
2 ESR C 4
= £
p´ ´
TPS51218
www.ti.com SLUS935B –MAY 2009– REVISED FEBRUARY 2012
SMALL SIGNAL MODEL
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 17.
Figure 17. Simplified Modulator Model
The output voltage is compared with internal reference voltage (ramp signal is ignored here for simplicity). The
PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
(1)
For loop stability, the 0-dB frequency, ƒ
0
, defined in Equation 2 need to be lower than 1/4 of the switching
frequency.
(2)
According to Equation 2, the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor's
chemistry. For example, specialty polymer capacitors (SP-CAP) have C
O
on the order of several 100 μF and
ESR in range of 10 mΩ. These makes f
0
on the order of 100 kHz or less and the loop is stable. However,
ceramic capacitors have an ƒ
0
of more than 700 kHz, which is not suitable for this modulator.
RAMP SIGNAL
The TPS51218 adds a ramp signal to the 0.7-V reference in order to improve its jitter performance. As described
in the previous section, the feedback voltage is compared with the reference information to keep the output
voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new
switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is
controlled to start with –7 mV at the beginning of ON-cycle and becomes 0 mV at the end of OFF-cycle in
continuous conduction steady state.
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