Datasheet
www.ti.com
Schematics
3 Schematics
Figure 1. TPS51206EVM-745, Schematic 1
5
SLUU515–August 2011 Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination
Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
DDR4