Datasheet

www.ti.com EVM Assembly Drawing and PCB Layout
Figure 27. TPS51206EVM-745 Internal Layer 1
Figure 28. TPS51206EVM-745 Internal Layer 2
23
SLUU515–August 2011 Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination
Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
DDR4