Datasheet

EVM Assembly Drawing and PCB Layout www.ti.com
Figure 25. TPS51206EVM-745 Top Layer Assembly Drawing
Figure 26. TPS51206EVM-745 Top Layer
22
Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination SLUU515–August 2011
Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
DDR4