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EVM Assembly Drawing and PCB Layout

7.7 DDR3 (0.75VTT) Bode Plot

Test condition: 5 Vin, VLDOIN = VDDQ = 1.5 V, VTT = VTTREF = 0.75 V, I

VTT

= 2 A Source Current

Phase Margin: 58.7Deg, Gain Margin: 7.6dB, Crossover Frequency: 1MHz

Figure 24. DDR3 Bode plot

8 EVM Assembly Drawing and PCB Layout

Figure 25 through Figure 30 show the design of the TPS51206EVM-745 printed-circuit board. The EVM

has been designed using a four-layer, 2-oz copper, printed-circuit board.

SLUU515–August 2011 Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination

Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and

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DDR4