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3 TPS51206EVM-745 Recommended Test Setup ....................................................................... 8

4 DDR2(0.9VTT) Load Regulation ........................................................................................ 11

5 DDR3 (0.75VTT) Load Regulation ...................................................................................... 11

6 DDR3L (0.675VTT) Load Regulation .................................................................................. 12

7 DDR4 (0.6VTT) Load Regulation........................................................................................ 12

8 DDR2 (0.9VTTREF) Load Regulation ................................................................................. 13

9 DDR3 (0.75VTTREF) Load Regulation................................................................................. 13

10 DDR3L (0.675VTTREF) Load Regulation ............................................................................. 14

11 DDR4 (0.6VTTREF) Load Regulation .................................................................................. 14

12 DDR2 (0.9VTT) Dropout Voltage ....................................................................................... 15

13 DDR3 (0.75VTT) Dropout Voltage ..................................................................................... 15

14 DDR3L (0.675VTT) Dropout Voltage .................................................................................. 16

15 DDR4 (0.6VTT) Dropout Voltage ....................................................................................... 16

16 DDR2 (0.9VTT) 1.8-A Sink/Source ..................................................................................... 17

17 DDR3 (0.75VTT) 1.5-A Sink/Source ................................................................................... 17

18 DDR3L (0.75VTT) 1.35-A Sink/Source ................................................................................ 18

19 DDR4 (0.6VTT) 1.2-A Sink/Source...................................................................................... 18

20 DDR3 (0.75VTT) S5 Enable Turnon ................................................................................... 19

21 DDR3 (0.75VTT) S5 Enable Turnoff ................................................................................... 19

22 DDR3 (0.75VTT) S3 Enable Turnon ................................................................................... 20

23 DDR3 (0.75VTT) S3 Enable Turnoff ................................................................................... 20

24 DDR3 Bode plot ........................................................................................................... 21

25 TPS51206EVM-745 Top Layer Assembly Drawing................................................................... 22

26 TPS51206EVM-745 Top Layer .......................................................................................... 22

27 TPS51206EVM-745 Internal Layer 1 .................................................................................. 23

28 TPS51206EVM-745 Internal Layer 2 ................................................................................... 23

29 TPS51206EVM-745 Bottom Layer ...................................................................................... 24

30 TPS51206EVM-745 Bottom Layer Assembly.......................................................................... 24

List of Tables

1 TPS51206EVM-745 Electrical Performance Specifications ........................................................... 3

2 Transient Load Selection .................................................................................................. 8

3 Source Transient Load Selection ......................................................................................... 9

4 Sink Transient Load Selection ............................................................................................ 9

5 S3, S5 Enable Selection ................................................................................................... 9

6 Functions of Each Test Point ............................................................................................ 10

7 Bill of Materials ............................................................................................................ 25

Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination SLUU515–August 2011

Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and

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