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Test Procedure

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6.2 DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Sink/Source

Current Transient

1. Remove VTT load from J3.

2. Remove V3 from TP3 (VTT) and TP5 (GND).

3. Add scope probe on TP3 (VTT) and TP5 (GND).

4. Remove jumper on Pin2 and Pin3 of J6 and put this jumper on Pin1 and Pin2 of J6.

5. Set switches S1, S2 to ON position.

6. TPS51206 is now operating at sink/source load transient.

7. Verify V2 and adjust VLDOIN if necessary.

8. Use scope probe at TP3 (VTT) and TP5 (GND) to monitor VTT load transient operation, and use

cursor to make measurement. The waveform is shown in Section 7.4.

9. Set switch S1, S2 to OFF position.

10. Decrease dc source 1.2 V to 0 V.

6.3 DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Loop Stability

Measurement

TPS51206EVM-745 contains an R4 (10-Ω) series resistor in the feedback loop for loop response analysis.

1. Set up EVM as described in Section 4 and Figure 3.

2. Connect isolation transformer to test points marked TP11 and TP10.

3. Connect input signal amplitude measurement probe (channel A) to TP11. Connect output signal

amplitude measurement probe (channel B) to TP10.

4. Connect ground lead of channel A and channel B to TP12.

5. Inject approximately 50-mV or less signal through the isolation transformer.

6. Sweep the frequency from 1 kHz to 1 MHz with 10-Hz or lower post filter. The control loop gain and

phase margin can be measured.

7. Disconnect isolation transformer from bode plot test points before making other measurements. Signal

injection into feedback may interfere with accuracy of other measurements.

6.4 List of Test Points

Table 6. Functions of Each Test Point

Test Points Name Description

TP1 VDD Device power supply input (3.3 V or 5 V)

TP2 GND Ground

TP3 VTT VTT Output

TP4 VDDQ VDDQSNS sense input, when VLDOIN is different from VDDQSNS

voltage

TP5 GND Ground

TP6 VLDOIN Power supply input for VTT/VTTREF

TP7 GND Ground

TP8 GND Ground

TP9 VTTREF VTTREF buffered reference output

TP10 CHB Input B for loop injection

TP11 CHA Input A for loop injection

TP12 GND Ground

TP13 GND Ground

TP14 GND Ground

TP15 CLK_IN Sink/source load transient timing signal

Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination SLUU515–August 2011

Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and

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