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User's Guide

SLUU515–August 2011

Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR

Termination Regulator With VTTREF Buffered Reference

for DDR2, DDR3, DDR3L, and DDR4

The TPS51206EVM-745 evaluation module (EVM) uses the TPS51206. The TPS51206 is a sink/source

double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically

designed for low-input voltage, low cost, low external component count systems where space is a key

consideration.

Contents

1 Description ................................................................................................................... 3

1.1 Typical Applications ................................................................................................ 3

1.2 Features ............................................................................................................. 3

2 Electrical Performance Specifications .................................................................................... 3

3 Schematics ................................................................................................................... 5

4 Test Setup ................................................................................................................... 7

4.1 Test Equipment ..................................................................................................... 7

4.2 Recommended Wire Gauge ...................................................................................... 7

4.3 Recommended Test Setup ....................................................................................... 7

5 Configurations ............................................................................................................... 8

5.1 Transient Load Selection .......................................................................................... 8

5.2 Source Transient Load Selection ................................................................................ 9

5.3 Sink Transient Load Selection ................................................................................... 9

5.4 S1, S2 Enable Selection .......................................................................................... 9

6 Test Procedure .............................................................................................................. 9

6.1 DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Source Load Regulation

........................................................................................................................ 9

6.2 DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Sink/Source Current

Transient ........................................................................................................... 10

6.3 DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Loop Stability

Measurement ..................................................................................................... 10

6.4 List of Test Points ................................................................................................ 10

6.5 Equipment Shutdown ............................................................................................ 11

7 Performance Data and Typical Characteristic Curves ................................................................ 11

7.1 VTT Load Regulation ............................................................................................ 11

7.2 VTTREF Load Regulation ....................................................................................... 13

7.3 VTT Dropout Voltage ............................................................................................. 15

7.4 VTT Sink/Source Load Transient ............................................................................... 17

7.5 DDR3(0.75VTT) S5 Enable Turnon/Turnoff ................................................................... 19

7.6 DDR3 (0.75VTT) S3 Enable Turnon/Turnoff .................................................................. 20

7.7 DDR3 (0.75VTT) Bode Plot ..................................................................................... 21

8 EVM Assembly Drawing and PCB Layout ............................................................................. 21

9 Bill of Materials ............................................................................................................. 25

List of Figures

1 TPS51206EVM-745, Schematic 1 ........................................................................................ 5

2 TPS51206EVM-745, Schematic 2 ........................................................................................ 6

SLUU515–August 2011 Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination

Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and

Submit Documentation Feedback

DDR4

Summary of content (27 pages)

PAGE 1
User's Guide SLUU515 – August 2011 Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and DDR4 The TPS51206EVM-745 evaluation module (EVM) uses the TPS51206. The TPS51206 is a sink/source double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low cost, low external component count systems where space is a key consideration.
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www.ti.com 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ....................................................................... DDR2(0.9VTT) Load Regulation ........................................................................................ DDR3 (0.75VTT) Load Regulation ...................................................................................... DDR3L (0.675VTT) Load Regulation .................................................................................
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Description www.ti.com 1 Description The TPS51206EVM-745 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR memory which covers DDR2 (0.9VTT), DDR3 (0.75VTT), DDR3L (0.675VTT) and DDR4 (0.6VTT) specifications with minimal external components. 1.1 Typical Applications • • 1.2 Features • • • • • • 2 DDR2/DDR3/DDR3L/DDR4 memory power supplies SSTL_18, SSTL_15, SSTL_135, and HSTL termination VDD voltage: support 5-V rail and 3.
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Electrical Performance Specifications www.ti.com Table 1. TPS51206EVM-745 Electrical Performance Specifications (1) (continued) Parameter Test Conditions Min Typ Max Units VTT and VTTREF Termination Voltage Tolerance VTT termination voltage tolerance VTT termination voltage tolerance IIVTTI < 2 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V –40 40 mV IIVTTI < 1.5 A, 1.2 V ≤ VVDDQSNS < 1.4 V –40 40 mV IIVTTREFI < 10 mA, 1.5 V ≤ VVDDQSNS ≤ 1.8 V 49% 51% IIVTTREFI < 10 mA, 1.2 V ≤ VVDDQSNS < 1.5 V 48.
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Schematics www.ti.com 3 Schematics Figure 1.
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Schematics www.ti.com Figure 2.
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Test Setup www.ti.com 4 Test Setup 4.1 Test Equipment 4.1.1 • • 4.1.2 • • • • 4.1.3 4.1.4 Voltage Source VDD: The VDD dc Source1 must be a 0-V to 10-V variable dc source capable of supplying 1 Adc. VLDOIN: The VLDOIN DC Source2 must be a 0-V to 10-V variable dc source capable of supplying 10 Adc.
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Configurations www.ti.com VLDOIN DC Source2 VDD DC Source1 + V2 - + - + VTT LOAD + V1 - + - + V4 - + V3 Figure 3. TPS51206EVM-745 Recommended Test Setup 5 Configurations All jumper selections must be made prior to applying power to the EVM. Users can configure this EVM per the following configurations. 5.1 Transient Load Selection The transient load selection can be set by J6. Default setting: Jumper shorts on Pin2 and Pin3 of J6 to disable transient load. Table 2.
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Test Procedure www.ti.com 5.2 Source Transient Load Selection The source transient load selection can be set by J7. Default setting: Jumper shorts on Pin1 and Pin2 of J7 to enable source transient load. Table 3. Source Transient Load Selection Jumper Set to 5.3 Transient Load 1-2 pin shorted Enable 2-3 pin shorted Disable Sink Transient Load Selection The sink transient load selection can be set by J8. Default setting: Jumper shorts on Pin1 and Pin2 of J8 to enable sink transient load. Table 4.
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Test Procedure 6.2 www.ti.com DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Sink/Source Current Transient 1. 2. 3. 4. 5. 6. 7. 8. Remove VTT load from J3. Remove V3 from TP3 (VTT) and TP5 (GND). Add scope probe on TP3 (VTT) and TP5 (GND). Remove jumper on Pin2 and Pin3 of J6 and put this jumper on Pin1 and Pin2 of J6. Set switches S1, S2 to ON position. TPS51206 is now operating at sink/source load transient. Verify V2 and adjust VLDOIN if necessary.
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Performance Data and Typical Characteristic Curves www.ti.com 6.5 Equipment Shutdown 1. Shut down VDD dc Source1 and VLDOIN dc Source2 2. Shut down VTT load. 3. Shut down oscilloscope. 7 Performance Data and Typical Characteristic Curves 7.1 VTT Load Regulation 0.92 VI = 3.3 V 0.915 VTT - Output Voltage - V 0.91 0.905 VI = 5 V 0.9 0.895 0.89 0.885 0.88 0.875 0.87 -2 -1.5 -1 -0.5 0 0.5 1 IVTT - Output Current - A 1.5 2 Figure 4. DDR2(0.9VTT) Load Regulation 0.78 VI = 3.
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Performance Data and Typical Characteristic Curves www.ti.com 0.7 VI = 3.3 V VTT - Output Voltage - V 0.69 0.68 VI = 5 V 0.67 0.66 0.65 0.64 -1.5 -1 -0.5 0 0.5 IVTT - Output Current - A 1 1.5 Figure 6. DDR3L (0.675VTT) Load Regulation 0.63 VTT - Output Voltage - V 0.62 VI = 3.3 V 0.61 0.6 VI = 5 V 0.59 0.58 0.57 0.56 -1.5 -1 -0.5 0 0.5 IVTT - Output Current - A 1 1.5 Figure 7. DDR4 (0.
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Performance Data and Typical Characteristic Curves www.ti.com 7.2 VTTREF Load Regulation 0.91 VTTREF - Output Voltage - V VI = 3.3 V 0.905 VI = 5 V 0.9 0.895 0.89 -10 -8 -6 -4 -2 0 2 4 6 IVTTREF - Output Current - mA 8 10 Figure 8. DDR2 (0.9VTTREF) Load Regulation 0.76 VTTREF - Output Voltage - V VI = 3.3 V 0.755 VI = 5 V 0.75 0.745 0.74 -10 -8 -6 -4 -2 0 2 4 6 IVTTREF - Output Current - mA 8 10 Figure 9. DDR3 (0.
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Performance Data and Typical Characteristic Curves www.ti.com 0.685 VTTREF - Output Voltage - V VI = 3.3 V 0.68 VI = 5 V 0.675 0.67 0.665 -10 -8 -6 -4 -2 0 2 4 6 IVTTREF - Output Current - mA 8 10 Figure 10. DDR3L (0.675VTTREF) Load Regulation 0.61 VTTREF - Output Voltage - V VI = 3.3 V 0.605 VI = 5 V 0.6 0.595 0.59 -10 -8 -6 -4 -2 0 2 4 6 IVTTREF - Output Current - mA 8 10 Figure 11. DDR4 (0.
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Performance Data and Typical Characteristic Curves www.ti.com 7.3 VTT Dropout Voltage 0.4 0.35 VI = 3.3 V Dropout Voltage - V 0.3 0.25 0.2 VI = 5 V 0.15 0.1 0.05 0 0 0.5 1 1.5 IVTT Output Current (A) 2 Figure 12. DDR2 (0.9VTT) Dropout Voltage 0.4 0.35 VI = 3.3 V Dropout Voltage - V 0.3 0.25 0.2 VI = 5 V 0.15 0.1 0.05 0 0 0.5 1 1.5 IVTT Output Current (A) 2 Figure 13. DDR3 (0.
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Performance Data and Typical Characteristic Curves www.ti.com 0.4 0.35 VI = 3.3 V Dropout Voltage - V 0.3 0.25 0.2 VI = 5 V 0.15 0.1 0.05 0 0 0.5 1 1.5 IVTT Output Current (A) 2 Figure 14. DDR3L (0.675VTT) Dropout Voltage 0.4 0.35 VI = 3.3 V Dropout Voltage - V 0.3 0.25 VI = 5 V 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 IVTT Output Current (A) 2 Figure 15. DDR4 (0.
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Performance Data and Typical Characteristic Curves www.ti.com 7.4 VTT Sink/Source Load Transient TPS1206EVM DDR2 VTT Sink and Source Current Transient Test condition: 5 Vin, VTT = VTTREF = 0.9 V IVTTREF = 0 A, IVTT Sink and Source current 1.8 A CH1: VTT CH2: VTTREF CH3: Transient Clock Figure 16. DDR2 (0.9VTT) 1.8-A Sink/Source TPS1206EVM DDR3 VTT Sink and Source Current Transient Test condition: 5 Vin, VTT = VTTREF = 0.75 V IVTTREF = 0 A, IVTT Sink and Source current 1.
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Performance Data and Typical Characteristic Curves TPS1206EVM DDR3L VTT Sink and Source Current Transient www.ti.com Test condition: 5 Vin, VTT = VTTREF = 0.675 V IVTTREF = 0 A, IVTT Sink and Source current 1.35 A CH1: VTT CH2: VTTREF CH3: Transient Clock Figure 18. DDR3L (0.75VTT) 1.35-A Sink/Source TPS1206EVM DDR4 VTT Sink and Source Current Transient Test condition: 5 Vin, VTT = VTTREF = 0.6 V IVTTREF = 0 A, IVTT Sink and Source current 1.
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Performance Data and Typical Characteristic Curves www.ti.com 7.5 DDR3(0.75VTT) S5 Enable Turnon/Turnoff TPS1206EVM DDR3 (1.5 V) S5 Enable Startup Test condition: 5 Vin, VTTREF = 0.75 V IVTTREF Sourcing 10 mA CH1: S5 CH2: S3 CH3: VTT CH4: VTTREF Figure 20. DDR3 (0.75VTT) S5 Enable Turnon TPS1206EVM DDR3 (1.5 V) S5 Enable Shutdown Test condition: 5 Vin, VTTREF = 0.75 V IVTTREF Sourcing 10 mA CH1: S5 CH2: S3 CH3: VTT CH4: VTTREF Figure 21. DDR3 (0.
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Performance Data and Typical Characteristic Curves 7.6 www.ti.com DDR3 (0.75VTT) S3 Enable Turnon/Turnoff TPS1206EVM DDR3 (1.5 V) S3 Enable Startup Test condition: 5 Vin, VTT = 0.75 V IVTT = 2 A CH1: S5 CH2: S3 CH3: VTT CH4: VTTREF Figure 22. DDR3 (0.75VTT) S3 Enable Turnon TPS1206EVM DDR3 (1.5 V) S3 Enable Shutdown Test condition: 5 Vin, VTT = 0.75 V IVTT = 1 A CH1: S5 CH2: S3 CH3: VTT CH4: VTTREF Figure 23. DDR3 (0.
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EVM Assembly Drawing and PCB Layout www.ti.com 7.7 DDR3 (0.75VTT) Bode Plot Test condition: 5 Vin, VLDOIN = VDDQ = 1.5 V, VTT = VTTREF = 0.75 V, IVTT = 2 A Source Current Phase Margin: 58.7Deg, Gain Margin: 7.6dB, Crossover Frequency: 1MHz Figure 24. DDR3 Bode plot 8 EVM Assembly Drawing and PCB Layout Figure 25 through Figure 30 show the design of the TPS51206EVM-745 printed-circuit board. The EVM has been designed using a four-layer, 2-oz copper, printed-circuit board.
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EVM Assembly Drawing and PCB Layout www.ti.com Figure 25. TPS51206EVM-745 Top Layer Assembly Drawing Figure 26.
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www.ti.com EVM Assembly Drawing and PCB Layout Figure 27. TPS51206EVM-745 Internal Layer 1 Figure 28.
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EVM Assembly Drawing and PCB Layout www.ti.com Figure 29. TPS51206EVM-745 Bottom Layer Figure 30.
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Bill of Materials www.ti.com 9 Bill of Materials Table 7 provides the EVM components list according to the schematics shown in Figure 1 and Figure 2. Table 7. Bill of Materials QTY RefDes Description MFR Part Number 3 C1, C14, C15 Capacitor, Ceramic, 0.1 µF, 10V, X7R, 20%, 0603 STD STD 3 C10, C11, C12 Capacitor, Ceramic, 10 µF, 10V, X5R, 20%, 0805 STD STD 3 C3, C4, C5 Capacitor, Ceramic, 10 µF, 10V, X5R, 20%, 0603 STD STD 1 C7 Capacitor, Ceramic, 0.
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Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.