Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulator - special purpose SON 10 (2x2)

UDG-11135

0.22 mF

0402

0.1 mF

0402

VLDOIN

VTT

PGND

VTTSNS

VDD

GND

VTTREF

VDDQSNS

Via to Ground Plane

Via for VTTSNS

VTTREFOutput

5-V or 3.3-V Supply Input

VTT Output

VDDQ Sense Input

VTT Power

Supply Input

Etch Beneath Component

10 mF

0603

10 mF

0603

TPS51206

SLUSAH1A –MAY 2011–REVISED OCTOBER 2013

www.ti.com

LAYOUT CONSIDERATIONS

Figure 25. PCB Layout Guideline

Consider the following before beginning a TPS51206 layout design.

• The input bypass capacitor for VLDOIN should be placed as close as possible to the terminal with short and

wide connections.

• The output capacitor for VTT should be placed close to the terminals (VTT and PGND) with short and wide

connection in order to avoid additional ESR and/or ESL trace inductance.

• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the

high current VTT power trace. In addition, VTTSNS trace should be routed away from high current trace, on

the separate layer is recommended. This configuration is strongly recommended to avoid additional ESR

and/or ESL. If sensing the voltage at the point of the load is required, it is recommended to attach the output

capacitor(s) at that point. In addition, it is recommended to minimize any additional ESR and/or ESL of ground

trace between the GND pin and the VTT capacitor(s).

• The GND pin (and the negative node of the VTTREF output capacitor) and PGND pins (and the negative

node of the VTT output capacitor) should be connected to the internal system ground planes (for better result,

use at least two internal ground planes) with multiple vias. Use as many vias as possible to reduce the

impedance between GND/PGND and the system ground plane.

• In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly

to the package thermal pad. The wide traces of the component and the side copper connected to the thermal

land pad help to dissipate heat. Numerous vias 0.33 mm in diameter connected from the thermal land to the

internal/solder side ground plane(s) should also be used to help dissipation. Please consult the TPS51206-

EVM User's Guide for more detailed layout recommendations.

Product Folder Links: TPS51206