Datasheet

TPS51200-Q1
SLUS984A –NOVEMBER 2009–REVISED APRIL 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)(2)
T
A
PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 125°C SON – DRC Reel of 3000 TPS51200QDRCRQ1 PSNQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE UNIT
VIN, VLDOIN, VOSNS, REFIN –0.3 to 3.6
Input voltage range
(2)
EN –0.3 to 6.5 V
PGND to GND –0.3 to 0.3
VO, REFOUT –0.3 to 3.6
Output voltage range
(2)
V
PGOOD –0.3 to 6.5
T
J
Operating junction temperature 150 °C
T
stg
Storage temperature –55 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
DISSIPATION RATINGS TABLE
(1)
DERATING FACTOR T
A
= 85°C
T
A
= 25°C
PACKAGE POWER RATING ABOVE T
A
= 25°C POWER RATING
10-Pin SON (DRC) 1.92 W 19 mW/°C 0.79 W
(1) PowerPAD size: 3.0 × 1.9 mm, 4 standard thermal vias. Based on the above environment, junction to thermal pad resistance θ
JP
is
10.24°C/W. Junction to ambient thermal resistance θ
JA
is 52.06°C/W.
THERMAL INFORMATION
TPS51200-Q1
THERMAL METRIC
(1)
UNIT
DRC (10 PINS)
θ
JA
Junction-to-ambient thermal resistance 51.6
θ
JCtop
Junction-to-case (top) thermal resistance 60.8
θ
JB
Junction-to-board thermal resistance 27.0
°C/W
ψ
JT
Junction-to-top characterization parameter 2.6
ψ
JB
Junction-to-board characterization parameter 27.2
θ
JCbot
Junction-to-case (bottom) thermal resistance 11.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Link(s): TPS51200-Q1