Datasheet

TPS51200-Q1
SLUS984A –NOVEMBER 2009–REVISED APRIL 2012 www.ti.com
Figure 5. Bode Plot for a Typical DDR3 Configuration
Figure 5 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200, where:
• V
IN
= 3.3 V
• V
VLDOIN
= 1.5 V
• V
VO
= 0.75 V
• I
IO
= 2 A
• 3 × 10-μF capacitors included
• ESR = 2.5 mΩ
• ESL = 800 pH
The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, the
gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.
Figure 6 shows the load regulation and Figure 7 shows the transient response for a typical DDR3 configuration.
When the regulator is subjected to ±1.5-A load step and release, the output voltage measurement shows no
difference between the dc and ac conditions.
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