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TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

3.3 V

PGOOD

SLP_S3

0.1 mF

VTTREF

VLDOIN

VTT

VDDQ

UDG-08025

TPS51200-Q1

www.ti.com

SLUS984A –NOVEMBER 2009–REVISED APRIL 2012

SINK/SOURCE DDR TERMINATION REGULATOR

Check for Samples: TPS51200-Q1

FEATURES

APPLICATIONS

• Qualified for Automotive Applications

• Memory Termination Regulator for DDR,

DDR2, DDR3, and Low Power DDR3/DDR4

• Input Voltage: Supports 2.5-V Rail and 3.3-V

Rail • Notebook/Desktop/Server

• VLDOIN Voltage Range: 1.1 V to 3.5 V • Telecom/Datacom, GSM Base Station, LCD-

TV/PDP-TV, Copier/Printer, Set-Top Box

• Sink/Source Termination Regulator Includes

DESCRIPTION

Droop Compensation

The TPS51200 is a sink/source Double Data Rate

• Requires Minimum Output Capacitance of 20-

(DDR) termination regulator specifically designed for

μF (typically 3 × 10-μF MLCCs) for Memory

low input voltage, low-cost, low-noise systems where

Termination Applications (DDR)

space is a key consideration.

• PGOOD to Monitor Output Regulation

The TPS51200 maintains a fast transient response

• EN Input

and only requires a minimum output capacitance of

• REFIN Input Allows for Flexible Input Tracking

20 μF. The TPS51200 supports a remote sensing

Either Directly or Through Resistor Divider

function and all power requirements for DDR, DDR2,

DDR3, and Low Power DDR3/DDR4 VTT bus

• Remote Sensing (VOSNS)

termination.

• ±10-mA Buffered Reference (REFOUT)

In addition, the TPS51200 provides an open-drain

• Built-in Soft Start, UVLO and OCL

PGOOD signal to monitor the output regulation and

• Thermal Shutdown

an EN signal that can be used to discharge VTT

• Meets DDR, DDR2 JEDEC Specifications;

during S3 (suspend to RAM) for DDR applications.

Supports DDR3 and Low-Power DDR3/DDR4

The TPS51200 is available in the thermally-efficient

VTT Applications

SON-10 PowerPAD package, and is rated both

• SON-10 PowerPAD™ Package

Green and Pb-free. It is specified from -40°C to

125°C.

STANDARD DDR APPLICATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

PAGE 1
TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V Rail VLDOIN Voltage Range: 1.1 V to 3.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage MIN MAX 2.375 3.500 –0.1 3.5 0.5 1.8 VO, PGOOD –0.1 3.5 REFOUT –0.1 1.8 PGND –0.1 0.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 × 10 μF and circuit shown in STANDARD DDR APPLICATION (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IIN Supply current TA = 25 °C, VEN = 3.3 V, No Load 0.7 1 TA = 25 °C, VEN = 0 V, VREFIN = 0, No Load 65 80 200 400 1 50 μA 0.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 × 10 μF and circuit shown in STANDARD DDR APPLICATION (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.2 2.3 2.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com DEVICE INFORMATION DRC PACKAGE (BOTTOM VIEW) TPS51200 (Bottom View) VOSNS 5 PGND 4 VO 3 VLDOIN 2 REFIN 1 6 REFOUT 7 EN 8 GND 9 PGOOD 10 VIN TERMINAL FUNCTIONS TERMINAL NAME EN GND NO. I/O DESCRIPTION 7 I For DDR VTT application, connect EN to SLP_S3. For any other application(s), use EN as the ON/OFF function. 8 – Ground.Signal ground. Connect to negative terminal of the output capacitor.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 FUNCTIONAL BLOCK DIAGRAM REFIN + 1 2.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com DETAILED DESCRIPTION VO SINK/SOURCE REGULATOR The TPS51200 is a sink/source tracking termination regulator specifically designed for low input voltage, lowcost, and low external component count systems where space is a key application parameter. The TPS51200 integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinking current.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 THERMAL SHUTDOWN The TPS51200 monitors the its junction temperature. If the device junction temperature exceeds its threshold value, (typically 150°C), the VO and REFOUT regulators are both shut off, discharged by the internal discharge MOSFETs. This shutdown is a non-latch protection.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com APPLICATION INFORMATION VIN CAPACITOR Add a ceramic capacitor, with a value between 1.0-μF and 4.7-μF, placed close to the VIN pin, to stabilize the bias supply (2.5- V rail or 3.3- V rail) from any parasitic impedance from the supply.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 3.3VIN VVDDQ = 1.5 V 0.390 V 0.370 V VLDOIN REFIN REFOUT (VTTREF) EN (S3_SLP) VVO = 0.75 V Tss VO TSS = PGOOD CO x VO IOOCL 2 ms UDG-08021 Figure 1. Typical Timing Diagram for S3 and pseudo-S5 Support 3.3VIN EN VLDOIN REFIN REFOUT (VTTREF) VO tSS determined by the SS time of VLDOIN VVO = 0.75 V PGOOD UDG-08020 2ms Figure 2.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com Output Tolerance Consideration for VTT DIMM Applications The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 3). The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 4 for typical characteristics for a single memory cell.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003). VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both dc and ac conditions The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com Figure 5. Bode Plot for a Typical DDR3 Configuration Figure 5 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200, where: • • • • • • • VIN = 3.3 V VVLDOIN = 1.5 V VVO = 0.75 V IIO = 2 A 3 × 10-μF capacitors included ESR = 2.5 mΩ ESL = 800 pH The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, the gain peaks because of the ESL effect.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 OUTPUT VOLTAGE vs OUTPUT CURRENT 790 VOUT – Output Voltage – mV VIN = 3.3 V 0°C 780 25°C 770 760 -40°C 750 740 730 720 710 700 -3 DDR3 -40°C 0°C 25°C 85°C -2 85°C -1 0 1 IOUT – Output Current – A 2 3 Figure 6. DC Regulaltion Figure 7. Transient LDO Design Guidelines VVO – Output Voltage – V The minimum input to output voltage difference (headroom) decides the lowest usable supply voltage Gm-driven to drive a certain load.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com THERMAL DESIGN Because the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN and VO times IO (IIO) current becomes the power dissipation as shown in Equation 2.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 For further information regarding the PowerPAD™ package and the recommended board layout, refer to the PowerPAD™ package application note (SLMA002). This document is available at www.ti.com. LAYOUT CONSIDERATIONS Consider the following points before starting the TPS51200 layout design. • The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide connections.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS For Figure 10 through Figure 24, 3 × 10-μF MLCCs (0805) are used on the output. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 940 1.30 VIN = 3.3 V 930 VOUT – Output Voltage – mV VOUT– Output Voltage – V 1.28 1.26 -40°C 0°C 1.24 1.22 DDR -40°C 0°C 25°C 85°C 1.20 920 910 -40°C 0°C 900 890 DDR2 -40°C 0°C 25°C 85°C 880 85°C 85°C 870 1.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 × 10-μF MLCCs (0805) are used on the output. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT CURRENT vs OUTPUT VOLTAGE 1.00 1.30 VIN = 2.5 V VIN = 2.5 V 1.25 1.20 VOUT – Output Voltage – V VOUT– Output Voltage – V 0.95 1.15 25°C 1.10 1.05 1.00 DDR 85°C -40°C 0°C 25°C 85°C 0.95 -40°C -40°C 0.90 0.85 0.80 85°C DDR2 25°C & 0°C -40°C 0°C 25°C 85°C 0.75 0°C 0.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 × 10-μF MLCCs (0805) are used on the output. REFOUT VOLTAGE vs REFOUT CURRENT REFOUT VOLTAGE vs REFOUT CURRENT 905 1.255 25°C 904 1.254 VREFOUT – Output Voltage – mV VREFOUT – Output Voltage – V 25°C 1.253 1.252 1.251 1.250 -40°C 1.249 DDR 1.248 1.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 × 10-μF MLCCs (0805) are used on the output. DROPOUT VOLTAGE vs OUTPUT CURRENT GAIN AND PHASE vs FREQUENCY 70 1.8 1.25 V 60 Phase 150 50 1.4 100 0.90 V 1.2 0.6 V 1.0 0.8 0.75 V 30 50 20 0 10 Gain -50 Phase – Degrees 40 Gain – dB VDRPOUT – Output Voltage – V 1.6 200 0 0.6 -100 -10 VOUT(V) 0.60 0.75 0.90 1.25 0.4 0.2 -30 1k 0 0 0.5 1.0 1.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com DESIGN EXAMPLES Design Example 1 This design example describes a 3.3-VIN, DDR2 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.8 V R2 10 kW VVLDOIN = VVDDQ = 1.8 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.9 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08028 Figure 25. 3.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 Design Example 2 This design example describes a 3.3-VIN, DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW C6 4.7 mF 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 SLP_S3 5 VOSNS REFOUT 6 VTTREF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF C5 0.1 mF UDG-08029 Figure 26. 3.3-VIN, DDR3 Configuration Table 3.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com Design Example 3 This design example describes a 2.5-VIN, DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 2.5 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08030 Figure 27. 2.5-VIN, DDR3 Configuration Table 4.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 Design Example 4 This design example describes a 3.3-VIN, LP DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.2 V R2 10 kW VVLDOIN = VVDDQ = 1.2 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.6 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08031 Figure 28. 3.3-VIN, LP DDR3 Configuration Table 5.
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TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com Design Example 5 This design example describes a 3.3-VIN, DDR3 Tracking Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF VIN 10 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF REFIN C4 1000 pF C3 10 mF VTTREF C5 0.1 mF UDG-08032 Figure 29. 3.3-VIN, DDR3 Tracking Configuration Table 6.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 Design Example 6 This design example describes a 3.3-VIN, LDO Configuration. R1 10 kW TPS51200 2.5 V 1 R2 3.86 kW VVLDOIN = VVLDOREF = 2.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVLDO = 1.8 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF ENABLE REFOUT C5 0.1 mF UDG-08033 Figure 30. 3.3-VIN, LDO Configuration Table 7.
PAGE 28
TPS51200-Q1 SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 www.ti.com Design Example 7 This design example describes a 3.3-VIN, DDR3 Configuration with LFP. R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VIN 10 REFIN C4 1000 pF R3 100 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF 3.3 VIN 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V R4(1) C1 10 mF C2 10 mF C3 10 mF SLP_S3 VTTREF C5 0.1 mF C9(1) UDG-08034 Figure 31. 3.
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TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 REVISION HISTORY Changes from Original (November, 2009) to Revision A • Page Added thermal table information for DRC package. .............................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS51200QDRCRQ1 ACTIVE Package Type Package Pins Package Drawing Qty SON DRC 10 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-3-260C-168 HR (4) -40 to 125 PSNQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS51200QDRCRQ1 Package Package Pins Type Drawing SON DRC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.3 1.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51200QDRCRQ1 SON DRC 10 3000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.